9.3.2.1 Device Noise Measurements

Setting CHnSET[2:0] = 001 sets the common-mode voltage of [(V_VREFP + V_VREFN) / 2] to both channel inputs. Use this setting to test inherent device noise in the user system.

9.3.2.2 Test Signals (TestP and TestN)

Setting CHnSET[2:0] = 101 provides internally-generated test signals for use in sub-system verification at power-up. The test signals are controlled through register settings (see the CONFIG2: Configuration Register 2 section for details). TEST_AMP controls the signal amplitude and TEST_FREQ controls the switching frequency of the test signal. The test signals are multiplexed and transmitted out of the device at the TESTP and TESTN pins. The INT_TEST register bit (in the CONFIG2: Configuration Register 2 section) deactivates the internal test signals so that the test signal can be driven externally. This feature allows the test or calibration of multiple devices with the same signal.

9.3.2.3 Temperature Sensor (TempP, TempN)

Setting CHnSET[2:0] = 100 sets the channel input to the temperature sensor. This sensor uses two internal diodes with one diode having a current density 16 times that of the other, as shown in Figure 17. The difference in diode current densities yields a difference in voltage that is proportional to absolute temperature.

Figure 17. Temperature Sensor Implementation

The internal device temperature tracks the PCB temperature closely because of the low thermal resistance of the package to the PCB. Self-heating of the ADS131E0x causes a higher reading than the temperature of the surrounding PCB. Setting the channel gain to 1 is recommended when the temperature measurement is taken.

The scale factor of Equation 3 converts the temperature reading to °C. Before using this equation, the temperature reading code must first be scaled to μV.

Equation 3.

9.3.2.4 Power-Supply Measurements (MVDDP, MVDDN)

Setting CHnSET[2:0] = 011 sets the channel inputs to different device supply voltages. For channels 1, 2, 5, 6, 7, and 8 (MVDDP – MVDDN) is [0.5 × (AVDD – AVSS)]; for channels 3 and 4 (MVDDP – MVDDN) is
DVDD / 4. Set the gain to 1 to avoid saturating the PGA when measuring power supplies.

Table 3. PGA Gain versus Bandwidth

9.3.4.1 Input Common-Mode Range

The usable input common-mode range of the analog front-end depends on various parameters, including the maximum differential input signal, supply voltage, and PGA gain. The common-mode range, V_CM, is defined in Equation 4:

Equation 4.

where

• V_{MAX_DIFF} = maximum differential signal at the PGA input and
• V_CM = common-mode voltage

For example:

If AVDD – AVSS = 3.3 V, gain = 2, and V_{MAX_DIFF} = 1000 mV,

Then 1.3 V < V_CM < 2.0 V

Table 4. CLKSEL Pin and CLK_EN Bit

9.4.1.1 Settling Time

The settling time (t_SETTLE) is the time required for the converter to output fully-settled data when the START signal is pulled high. When START is pulled high, DRDY is also pulled high. The next DRDY falling edge indicates that data are ready. Figure 31 shows the timing diagram and Table 5 shows the settling time for different data rates as a function of t_CLK. The settling time depends on f_CLK and the decimation ratio (controlled by the DR[2:0] bits in the CONFIG1 register). When the initial settling time has passed, the DRDY falling edge occurs at the set data rate, t_DR. If data is not read back on DOUT and the output shift register needs to update, DRDY goes high for 4 t_CLK before returning back low indicating new data is ready. Note that when START is held high and there is a step change in the input signal, 3 × t_DR is required for the filter to settle to the new value. Settled data are available on the fourth DRDY pulse.

Figure 31. Settling Time

9.4.1.2 Input Signal Step

When the device is converting and there is a step change on the input signal, a delay of 3 t_DR is required for the output data to settle. Settled data are available on the fourth DRDY pulse. Data are available to read at each DRDY low transition prior to the 4th DRDY pulse, but are recommended to be ignored. Figure 32 shows the required wait time for complete settling for an input step or input transient event on the analog input.

Figure 32. Settling Time for the Input Transient

Table 6. Timing Characteristics for Figure 34⁽¹⁾

9.4.5.1 Data Ready (DRDY)

DRDY is an output signal which transitions from high to low indicating new conversion data are ready. The CS signal has no effect on the data ready signal. DRDY behavior is determined by whether the device is in RDATAC mode or the RDATA command is used to read data on demand. (See the RDATAC: Start Read Data Continuous Mode and RDATA: Read Data subsections of the SPI Command Definitions section for further details).

When reading data with the RDATA command, the read operation can overlap the next DRDY occurrence without data corruption.

The START pin or the START command places the device either in normal data capture mode or pulse data capture mode.

Figure 35 shows the relationship between CS, DRDY, DOUT, and SCLK during data retrieval (in case of an ADS131E0x). DOUT is latched out at the SCLK rising edge. DRDY is pulled high at the SCLK falling edge. Note that DRDY goes high on the first SCLK falling edge, regardless of whether data are being retrieved from the device or a command is being sent through the DIN pin.

Figure 35. DRDY Behavior with Data Retrieval

The DRDY signal is cleared on the first SCLK falling edge regardless of the state of CS. This condition must be taken into consideration if the SPI bus is used to communicate with other devices on the same bus. Figure 36 shows a behavior diagram for DRDY when SCLKs are sent with CS high. Figure 36 shows that no data are clocked out, but the DRDY signal is cleared.

Figure 36. DRDY and SCLK Behavior when CS is High

9.4.5.2 Reading Back Data

Data retrieval can be accomplished in one of two methods:

1. RDATAC: the read data continuous command sets the device in a mode that reads data continuously without sending commands. See the RDATAC: Start Read Data Continuous Mode section for more details.
2. RDATA: the read data command requires that a command is sent to the device to load the output shift register with the latest data. See the RDATA: Read Data section for more details.

Conversion data are read by shifting data out on DOUT. The MSB of the data on DOUT is clocked out on the first SCLK rising edge. DRDY returns high on the first SCLK falling edge. DIN should remain low for the entire read operation.

9.4.5.3 Status Word

A status word precedes data readback and provides information on the state of the ADS131E0x. The status word is 24 bits long and contains the values for FAULT_STATP, FAULT_STATN, and the GPIO data bits. The content alignment is shown in Figure 37.

Figure 37. Status Word Content

9.4.5.4 Readback Length

The number of bits in the data output depends on the number of channels and the number of bits per channel. The data format for each channel data are twos complement and MSB first.

For the ADS131E0x with 32-kSPS and 64-kSPS data rates, the number of data bits is: 24 status bits + 16 bits per channel × 8 channels = 152 bits.

For all other data rates, the number of data bits is: 24 status bits + 24 bits per channel × 8 channels = 216 bits.

When channels are powered down using the user register setting, the corresponding channel output is set to 0. However, the sequence of channel outputs remains the same.

The ADS131E0x also provides a multiple data readback feature. Data can be read out multiple times by simply providing more SCLKs, in which case the MSB data byte repeats after reading the last byte. The DAISY_IN bit in the CONFIG1 register must be set to 1 for multiple read backs.

Table 7. 16-Bit Ideal Output Code versus Input Signal

Table 8. 24-Bit Ideal Output Code versus Input Signal

The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT. The interface is used to read conversion data, read and write registers, and control the ADS131E0x operation. The DRDY output is used as a status signal to indicate when ADC data are ready for readback. DRDY goes low when new data are available.

9.5.2.1 Chip Select (CS)

The CS pin activates SPI communication. CS must be low before data transactions and must stay low for the entire SPI communication period. When CS is high, the DOUT pin enters a high-impedance state. Therefore, reading and writing to the serial interface are ignored and the serial interface is reset. DRDY pin operation is independent of CS. DRDY still indicates that a new conversion has completed and is forced high as a response to SCLK, even if CS is high.

Taking CS high deactivates only the SPI communication with the device and the serial interface is reset. Data conversion continues and the DRDY signal can be monitored to check if a new conversion result is ready. A master device monitoring the DRDY signal can select the appropriate slave device by pulling the CS pin low. After the serial communication is finished, always wait four or more t_CLK cycles before taking CS high.

9.5.2.2 Serial Clock (SCLK)

SCLK provides the clock for serial communication. SCLK is a Schmitt-trigger input, but TI recommends keeping SCLK as free from noise as possible to prevent glitches from inadvertently shifting the data. Data are shifted into DIN on the falling edge of SCLK and shifted out of DOUT on the rising edge of SCLK.

The absolute maximum SCLK limit is specified in Figure 1. When shifting in commands with SCLK, make sure that the entire set of SCLKs is issued to the device. Failure to do so can result in the device serial interface being placed into an unknown state requiring CS to be taken high to recover.

For a single device, the minimum speed required for SCLK depends on the number of channels, number of bits of resolution, and output data rate. (For multiple devices, see the Multiple Device Configuration section.)

For example, if the ADS131E0x is used with an 8-kSPS mode (24-bit resolution), the minimum SCLK speed is 1.755 MHz to shift out all the data.

Data retrieval can be accomplished either by placing the device in RDATAC mode or by issuing an RDATA command for data on demand. The SCLK rate limitation in Equation 9 applies to RDATAC. For the RDATA command, the limitation applies if data must be read in between two consecutive DRDY signals. Equation 9 assumes that there are no other commands issued in between data captures.

9.5.2.3 Data Input (DIN)

DIN is used along with SCLK to send data to the device. Data on DIN are shifted into the device on the falling edge of SCLK.

The communication of this device is full-duplex in nature. The device monitors commands shifted in even when data are being shifted out. Data that are present in the output shift register are shifted out when sending in a command. Therefore, make sure that whatever is being sent on the DIN pin is valid when shifting out data. When no command is to be sent to the device when reading out data, send the NOP command on DIN. Make sure that the t_SDECODE timing is met in the Sending Multibyte Commands section when sending multiple byte commands on DIN.

9.5.2.4 Data Output (DOUT)

DOUT is used with SCLK to read conversion and register data from the device. Data are clocked out on the rising edge of SCLK, MSB first. DOUT goes to a high-impedance state when CS is high. In read data continuous mode (see the SPI Command Definitions section for more details), the DOUT output line can also be used to indicate when new data are available. If CS is low when new data are ready, a high-to-low transition on the DOUT line occurs synchronously with a high-to-low transition on DRDY, as shown in Figure 38. This feature can be used to minimize the number of connections between the device and system controller.

Figure 38. Using DOUT as DRDY

Table 9. Command Definitions

9.5.3.1 Sending Multibyte Commands

The ADS131E0x serial interface decodes commands in bytes and requires 4 t_CLK cycles to decode and execute each command. Therefore, when sending multi-byte commands (such as RREG or WREG), a 4 t_CLK period must separate the end of one byte (or command) and the next.

Assuming CLK is 2.048 MHz, then t_SDECODE (4 t_CLK) is 1.96 µs. When SCLK is 16 MHz, one byte can be transferred in 0.5 µs. This byte transfer time does not meet the t_SDECODE specification; therefore, a delay of 1.46 µs (1.96 µs – 0.5 µs) must be inserted after the first byte and before the second byte. If SCLK is 4 MHz, one byte is transferred in 2 µs. Because this transfer time exceeds the t_SDECODE specification (2 µs > 1.96 µs), the processor can send subsequent bytes without delay.

9.5.3.2 WAKEUP: Exit STANDBY Mode

The WAKEUP command exits the low-power standby mode; see the STANDBY: Enter STANDBY Mode section. Be sure to allow enough time for all circuits in standby mode to power-up (see the Electrical Characteristics table for details). There are no SCLK rate restrictions for this command and it can be issued at any time. There are no SCLK rate restrictions for this command and can be issued at any time. Any following commands must be sent after a delay of 4 t_CLK cycles.

9.5.3.3 STANDBY: Enter STANDBY Mode

The STANDBY command enters low-power standby mode. All circuits in the device are powered down except for the reference section. The standby mode power consumption is specified in the Electrical Characteristics table. There are no SCLK rate restrictions for this command and can be issued at any time. Do not send any other commands other than the WAKEUP command after the device enters standby mode.

9.5.3.4 RESET: Reset Registers to Default Values

The RESET command resets the digital filter and returns all register settings to their default values; see the Reset (RESET) section for more details. There are no SCLK rate restrictions for this command and can be issued at any time. 18 t_CLK cycles are required to execute the RESET command. Avoid sending any commands during this time.

9.5.3.5 START: Start Conversions

The START command starts data conversions. Tie the START pin low to control conversions by the START and STOP commands. If conversions are in progress, this command has no effect. The STOP command is used to stop conversions. If the START command is immediately followed by a STOP command, then there must be a gap of 4 t_CLK cycle delay between them. The current conversion completes before further conversions are halted. There are no SCLK rate restrictions for this command and can be issued at any time.

9.5.3.6 STOP: Stop Conversions

The STOP command stops conversions. Tie the START pin low to control conversions by command. When the STOP command is sent, the conversion in progress completes and further conversions are stopped. If conversions are already stopped, this command has no effect. There are no SCLK rate restrictions for this command and can be issued at any time.

9.5.3.7 OFFSETCAL: Channel Offset Calibration

The OFFSETCAL command cancels the offset of each channel. The OFFSETCAL command is recommended to be issued every time there is a change in PGA gain settings.

When the OFFSETCAL command is issued, the device configures itself to the lowest data rate (DR[2:0] = 110, 1 kSPS) and performs the following steps for each channel:

• Short the analog inputs of each channel together and connect them to mid-supply [(AVDD + AVSS) / 2]
• Reset the digital filter (requires a filter settling time = 4 t_DR)
• Collect 16 data points for calibration = 15 t_DR

Total calibration time = (19 t_DR × 8) + 1 ms = 153 ms.

9.5.3.8 RDATAC: Start Read Data Continuous Mode

The RDATAC command enables read data continuous mode. In this mode, conversion data are retrieved from the device without the need to issue subsequent RDATA commands. This mode places the conversion data in the output register with every DRDY falling edge so that the data can be shifted out directly with the following SCLKs. Shift out all data from the device before data are updated with a new DRDY falling edge to avoid losing data. The read data continuous mode is the device default mode; the device defaults to this mode on powerup. Figure 39 shows the ADS131E0x data output protocol when using RDATAC mode.

NOTE:

X SCLKs = (N bits)(8 channels) + 24 bits. N-bit is dependent upon the DR[2:0] registry bit settings (N = 16 or 24).

Figure 39. ADS131E0x SPI Bus Data Output (Eight Channels)

RDATAC mode is cancelled by the Stop Read Data Continuous command. If the device is in RDATAC mode, a SDATAC command must be issued before any other commands can be sent to the device. There are no SCLK rate restrictions for this command. However, subsequent data retrieval SCLKs or the SDATAC command should wait at least 4 t_CLK cycles before completion. RDATAC timing is shown in Figure 40. There is a keep out zone of 4 t_CLK cycles around the DRDY pulse where this command cannot be issued in. If no data are retrieved from the device and CS is held low, a high-to-low DOUT transition occurs synchronously with DRDY. To retrieve data from the device after the RDATAC command is issued, make sure either the START pin is high or the START command is issued. Figure 40 shows the recommended way to use the RDATAC command. Read data continuous mode is ideally-suited for applications such as data loggers or recorders where registers are set one time and do not need to be reconfigured.

1. t_UPDATE = 4 / f_CLK. Do not read data during this time.

Figure 40. Reading Data in RDATAC Mode

9.5.3.9 SDATAC: Stop Read Data Continuous Mode

The SDATAC command cancels the Read Data Continuous mode. There are no SCLK rate restrictions for this command, but the next command must wait for 4 t_CLK cycles before completion.

9.5.3.10 RDATA: Read Data

The RDATA command loads the output shift register with the latest data when not in Read Data Continuous mode. Issue this command after DRDY goes low to read the conversion result. There are no SCLK rate restrictions for this command, and there is no wait time needed for the subsequent commands or data retrieval SCLKs. To retrieve data from the device after the RDATA command is issued, make sure either the START pin is high or the START command is issued. When reading data with the RDATA command, the read operation can overlap the next DRDY occurrence without data corruption. RDATA can be sent multiple times after new data are available, thus supporting multiple data readback. Figure 41 illustrates the recommended way to use the RDATA command. RDATA is best suited for systems where register settings must be read or the user does not have precise control over timing. Reading data using the RDATA command is recommended to avoid data corruption when the DRDY signal is not monitored.

Figure 41. RDATA Usage

9.5.3.11 RREG: Read from Register

The RREG command reads the contents of one or more device configuration registers. The Register Read command is a two-byte command followed by the register data output. The first byte contains the command and register address. The second command byte specifies the number of registers to read – 1.

First command byte: 001r rrrr, where r rrrr is the starting register address.

Second command byte: 000n nnnn, where n nnnn is the number of registers to read – 1.

The 17th SCLK rising edge of the operation clocks out the MSB of the first register, as shown in Figure 42. When the device is in read data continuous mode, an SDATAC command must be issued before the RREG command can be issued. The RREG command can be issued any time. However, because this command is a multi-byte command, there are SCLK rate restrictions depending on how the SCLKs are issued to meet the t_SDECODE timing. See the Serial Clock (SCLK) subsection of the SPI Interface section for more details. Note that CS must be low for the entire command.

Figure 42. RREG Command Example: Read Two Registers Starting from Register 00h (ID Register)
(BYTE 1 = 0010 0000, BYTE 2 = 0000 0001)

9.5.3.12 WREG: Write to Register

The WREG command writes data to one or more device configuration registers. The Register Write command is a two-byte command followed by the register data input. The first byte contains the command and register address. The second command byte specifies the number of registers to write – 1.

First command byte: 010r rrrr, where r rrrr is the starting register address.

Second command byte: 000n nnnn, where n nnnn is the number of registers to write – 1.

After the command bytes, the register data follows (in MSB-first format), as shown in Figure 43. For multiple register writes across reserved registers (0Dh–11h), these registers must be included in the register count and the default setting of the reserved register must be written. The WREG command can be issued at any time. However, because this command is a multi-byte command, there are SCLK rate restrictions depending on how the SCLKs are issued to meet the t_SDECODE timing. See the Figure 1 for more details. CS must be low for the entire command.

Figure 43. WREG Command Example: Write Two Registers Starting from 00h (ID Register)
(BYTE 1 = 0100 0000, BYTE 2 = 0000 0001)

9.6.1.1 ID: ID Control Register (Factory-Programmed, Read-Only) (address = 00h) [reset = xxh]

This register is programmed during device manufacture to indicate device characteristics.

9.6.1.2 CONFIG1: Configuration Register 1 (address = 01h) [reset = 91h]

This register configures daisy chain, the clock setting, and each ADC channel sample rate.

9.6.1.3 CONFIG2: Configuration Register 2 (address = 02h) [reset = E0h]

This register configures the test signal generation; see the Input Multiplexer section for more details.

9.6.1.4 CONFIG3: Configuration Register 3 (address = 03h) [reset = 40]

This register configures the reference and internal amplifier operation.

9.6.1.5 FAULT: Fault Detect Control Register (address = 04h) [reset = 00h]

This register configures the fault detection operation.

9.6.1.6 CHnSET: Individual Channel Settings (address = 05h to 0Ch) [reset = 10h]

This register configures the power mode, PGA gain, and multiplexer settings for the channels; see the Input Multiplexer section for details. CHnSET are similar to CH1SET, corresponding to the respective channels (see Table 10).

9.6.1.7 FAULT_STATP: Fault Detect Positive Input Status (address = 12h) [reset = 00h]

This register stores the status of whether the positive input on each channel has a fault or not. Faults are determined by comparing the input pin to a threshold set by Table 16; see the Input Out-of-Range Detection section for details.

9.6.1.8 FAULT_STATN: Fault Detect Negative Input Status (address = 13h) [reset = 00h]

This register stores the status of whether the negative input on each channel has a fault or not. Faults are determined by comparing the input pin to a threshold set by Table 16; see the Input Out-of-Range Detection section for details.

9.6.1.9 GPIO: General-Purpose IO Register (address = 14h) [reset = 0Fh]

This register controls the format and state of the four GPIO pins.