SBAS561C June   2012  – January 2017 ADS131E04 , ADS131E06 , ADS131E08

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Measurements
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Electromagnetic Interference (EMI) Filter
      2. 9.3.2  Input Multiplexer
        1. 9.3.2.1 Device Noise Measurements
        2. 9.3.2.2 Test Signals (TestP and TestN)
        3. 9.3.2.3 Temperature Sensor (TempP, TempN)
        4. 9.3.2.4 Power-Supply Measurements (MVDDP, MVDDN)
      3. 9.3.3  Analog Input
      4. 9.3.4  PGA Settings and Input Range
        1. 9.3.4.1 Input Common-Mode Range
      5. 9.3.5  ΔΣ Modulator
      6. 9.3.6  Clock
      7. 9.3.7  Digital Decimation Filter
      8. 9.3.8  Voltage Reference
      9. 9.3.9  Input Out-of-Range Detection
      10. 9.3.10 General-Purpose Digital I/O (GPIO)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Start
        1. 9.4.1.1 Settling Time
        2. 9.4.1.2 Input Signal Step
      2. 9.4.2 Reset (RESET)
      3. 9.4.3 Power-Down (PWDN)
      4. 9.4.4 Continuous Conversion Mode
      5. 9.4.5 Data Retrieval
        1. 9.4.5.1 Data Ready (DRDY)
        2. 9.4.5.2 Reading Back Data
        3. 9.4.5.3 Status Word
        4. 9.4.5.4 Readback Length
    5. 9.5 Programming
      1. 9.5.1 Data Format
      2. 9.5.2 SPI Interface
        1. 9.5.2.1 Chip Select (CS)
        2. 9.5.2.2 Serial Clock (SCLK)
        3. 9.5.2.3 Data Input (DIN)
        4. 9.5.2.4 Data Output (DOUT)
      3. 9.5.3 SPI Command Definitions
        1. 9.5.3.1  Sending Multibyte Commands
        2. 9.5.3.2  WAKEUP: Exit STANDBY Mode
        3. 9.5.3.3  STANDBY: Enter STANDBY Mode
        4. 9.5.3.4  RESET: Reset Registers to Default Values
        5. 9.5.3.5  START: Start Conversions
        6. 9.5.3.6  STOP: Stop Conversions
        7. 9.5.3.7  OFFSETCAL: Channel Offset Calibration
        8. 9.5.3.8  RDATAC: Start Read Data Continuous Mode
        9. 9.5.3.9  SDATAC: Stop Read Data Continuous Mode
        10. 9.5.3.10 RDATA: Read Data
        11. 9.5.3.11 RREG: Read from Register
        12. 9.5.3.12 WREG: Write to Register
    6. 9.6 Register Map
      1. 9.6.1 Register Descriptions
        1. 9.6.1.1 ID: ID Control Register (Factory-Programmed, Read-Only) (address = 00h) [reset = xxh]
        2. 9.6.1.2 CONFIG1: Configuration Register 1 (address = 01h) [reset = 91h]
        3. 9.6.1.3 CONFIG2: Configuration Register 2 (address = 02h) [reset = E0h]
        4. 9.6.1.4 CONFIG3: Configuration Register 3 (address = 03h) [reset = 40]
        5. 9.6.1.5 FAULT: Fault Detect Control Register (address = 04h) [reset = 00h]
        6. 9.6.1.6 CHnSET: Individual Channel Settings (address = 05h to 0Ch) [reset = 10h]
        7. 9.6.1.7 FAULT_STATP: Fault Detect Positive Input Status (address = 12h) [reset = 00h]
        8. 9.6.1.8 FAULT_STATN: Fault Detect Negative Input Status (address = 13h) [reset = 00h]
        9. 9.6.1.9 GPIO: General-Purpose IO Register (address = 14h) [reset = 0Fh]
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Unused Inputs and Outputs
      2. 10.1.2 Setting the Device Up for Basic Data Capture
      3. 10.1.3 Multiple Device Configuration
        1. 10.1.3.1 Synchronizing Multiple Devices
        2. 10.1.3.2 Standard Configuration
        3. 10.1.3.3 Daisy-Chain Configuration
      4. 10.1.4 Power Monitoring Specific Applications
      5. 10.1.5 Current Sensing
      6. 10.1.6 Voltage Sensing
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power-Up Timing
    2. 11.2 Recommended External Capacitor Values
    3. 11.3 Device Connections for Unipolar Power Supplies
    4. 11.4 Device Connections for Bipolar Power Supplies
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resource
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Power-supply voltage AVDD to AVSS –0.3 5.5 V
AVSS to DGND –3 0.2
DVDD to DGND –0.3 3.9
Analog input voltage Analog input to AVSS AVSS – 0.3 AVDD + 0.3 V
Digital input voltage Digital input to DVDD DGND – 0.3 DVDD + 0.3 V
Input current Momentary –100 100 mA
Continuous, all other pins except power-supply pins –10 10
Temperature Junction, TJ 150 °C
Storage, Tstg –60 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
POWER SUPPLY
AVDD Analog power supply AVDD to AVSS 2.7 5.0 5.25 V
DVDD Digital power supply DVDD to DGND 1.7 1.8 3.6 V
Analog to digital supply AVDD to DVDD –2.1 3.6 V
ANALOG INPUTS
VIN Differential input voltage VIN = V(INxP) – V(INxN) –VREF / Gain VREF / Gain V
VCM Common-mode input voltage VCM = (V(INxP) – V(INxN)) / 2 See the Input Common-Mode Range section V
VOLTAGE REFERENCE INPUTS
VREF Reference input voltage AVDD = 3 V, VREF = (VVREFP – VVREFN) 2 2.5 AVDD V
AVDD = 5 V, VREF = (VVREFP – VVREFN) 2 4 AVDD V
VREFN Negative reference input AVSS V
VREFP Positive input AVDD – 3 AVSS + 2.5 AVDD V
EXTERNAL CLOCK SOURCE
fCLK Master clock rate CLKSEL pin = 0,
(AVDD – AVSS) = 3 V		 1.7 2.048 2.25 MHz
CLKSEL pin = 0,
(AVDD – AVSS) = 5 V		 1.0 2.048 2.25
DIGITAL INPUTS
Input voltage DGND – 0.1 DVDD + 0.1 V
TEMPERATURE RANGE
TA Operating ambient temperature –40 105 °C

7.4 Thermal Information

THERMAL METRIC(1) ADS131E0x UNIT
PAG (TQFP)
64 PINS
RθJA Junction-to-ambient thermal resistance 35 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 31 °C/W
RθJB Junction-to-board thermal resistance 26 °C/W
ψJT Junction-to-top characterization parameter 0.1 °C/W
ψJB Junction-to-board characterization parameter NA °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance NA °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

Minimum and maximum specifications apply from –40°C to +105°C. Typical specifications are at 25°C. All specifications are at DVDD = 1.8 V, AVDD = 3 V, AVSS = 0 V, VREF = 2.4 V, external fCLK = 2.048 MHz, data rate = 8 kSPS, and gain = 1, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Ci Input capacitance 20 pF
IIB Input bias current PGA output in normal range 5 nA
DC input impedance 200 MΩ
PGA PERFORMANCE
Gain settings 1, 2, 4, 8, 12
BW Bandwidth See Table 3
ADC PERFORMANCE
DR Data rate fCLK = 2.048 MHz 1 64 kSPS
Resolution DR = 1 kSPS, 2 kSPS, 4 kSPS, 8 kSPS, and 16 kSPS 24 Bits
DR = 32 kSPS and 64 kSPS 16 Bits
CHANNEL PERFORMANCE (DC PERFORMANCE)
INL Integral nonlinearity Full-scale, best fit 10 ppm
Dynamic range G = 1 105 dB
Gain settings other than 1 See the Noise Measurements section
EO Offset error 350 μV
Offset error drift 0.65 μV/°C
EG Gain error Excluding voltage reference error 0.1%
Gain drift Excluding voltage reference drift 3 ppm/°C
Gain match between channels 0.2 % of FS
CHANNEL PERFORMANCE (AC PERFORMANCE)
CMRR Common-mode rejection ratio fCM = 50 Hz and 60 Hz(1) –110 dB
PSRR Power-supply rejection ratio fPS = 50 Hz and 60 Hz –80 dB
Crosstalk fIN = 50 Hz and 60 Hz –110 dB
Accuracy 3000:1 dynamic range with a 1-second measurement
(VRMS / IRMS)		 AVDD = 3 V, VREF = 2.4 V 0.04%
AVDD = 5 V, VREF = 4 V 0.025%
SNR Signal-to-noise ratio fIN = 50 Hz and 60 Hz, gain = 1 107 dB
THD Total harmonic distortion 10 Hz, –0.5 dBFs –93 dB
INTERNAL REFERENCE
VREF Output voltage TA = 25°C, VREF = 2.4 V 2.394 2.4 2.406 V
TA = 25°C, VREF = 4 V 4 V
VREF accuracy ±0.2%
Temperature drift TA = –40°C to +105°C 20 ppm/°C
Start-up time Settled to 0.2% 150 ms
EXTERNAL REFERENCE
Input impedance 6 kΩ
INTERNAL OSCILLATOR
Accuracy ±2%
TA = 25°C ±0.5%
TA = –40°C to 105°C 2.5%
Internal oscillator clock frequency Nominal frequency 2.048 MHz
Internal oscillator start-up time 20 μs
Internal oscillator power consumption 120 μW
FAULT DETECT AND ALARM
Comparator threshold accuracy ±30 mV
OPERATIONAL AMPLIFIER
Integrated noise 0.1 Hz to 250 Hz 9 µVRMS
Noise density 2 kHz 120 nV/√Hz
GBP Gain bandwidth product 50 kΩ || 10-pF load 100 kHz
SR Slew rate 50 kΩ || 10-pF load 0.25 V/µs
Load current 50 µA
THD Total harmonic distortion fIN = 100 Hz 70 dB
Common-mode input range AVSS + 0.7 AVDD – 0.3 V
Quiescent power consumption 20 µA
SYSTEM MONITORS
Supply reading error Analog 2%
Digital 2%
Device wake up From power-up to DRDY low 150 ms
STANDBY mode 31.25 µs
Temperature sensor reading Voltage TA = 25°C 145 mV
Coefficient 490 μV/°C
SELF-TEST SIGNAL
Signal frequency See the Register Map section for settings fCLK / 221 Hz
fCLK / 220
Signal voltage See the Register Map section for settings ±1 mV
±2
DIGITAL INPUT AND OUTPUT (DVDD = 1.8 V to 3.6 V)
VIH Logic level,
input voltage		 High 0.8 DVDD DVDD+0.1 V
VIL Low –0.1 0.2 DVDD V
VOH Logic level,
output voltage		 High IOH = –500 µA 0.9 DVDD V
VOL Low IOL = +500 µA 0.1 DVDD V
IIN Input current 0 V < VDigitalInput < DVDD –10 10 μA
SUPPLY CURRENT (OPERATIONAL AMPLIFIER TURNED OFF)
IAVDD Normal mode AVDD – AVSS = 3 V 5.1 mA
AVDD – AVSS = 5 V 5.8 mA
IDVDD DVDD = 3.3 V 1 mA
DVDD = 1.8 V 0.4 mA
POWER DISSIPATION (ANALOG SUPPLY = 3 V)
Quiescent power dissipation ADS131E04 Normal mode 9.3 10.2 mW
Power-down mode 10 µW
Standby mode 2 mW
ADS131E06 Normal mode 12.7 13.5 mW
Power-down mode 10 µW
Standby mode 2 mW
ADS131E08 Normal mode 16 17.6 mW
Power-down mode 10 µW
Standby mode 2 mW
POWER DISSIPATION (ANALOG SUPPLY = 5 V)
Quiescent power dissipation ADS131E04 Normal mode 18 mW
Power-down mode 20 µW
Standby mode 4.2 mW
ADS131E06 Normal mode 24.3 mW
Power-down mode 20 µW
Standby mode 4.2 mW
ADS131E08 Normal mode 29.7 mW
Power-down mode 20 µW
Standby mode 4.2 mW
(1) CMRR is measured with a common-mode signal of (AVSS + 0.3 V) to (AVDD – 0.3 V). The values indicated are the minimum of the eight channels.

7.6 Timing Requirements

over operating ambient temperature range and DVDD = 1.7 V to 3.6 V (unless otherwise noted)
2.7 V ≤ DVDD ≤ 3.6 V 1.7 V ≤ DVDD ≤ 2.0 V UNIT
MIN MAX MIN MAX
tCLK Master clock period 444 588 444 588 ns
tCSSC Delay time, first SCLK rising edge after CS falling edge 6 17 ns
tSCLK SCLK period 50 66.6 ns
tSPWH, L Pulse duration, SCLK high or low 15 25 ns
tDIST Setup time, DIN valid before SCLK falling edge 10 10 ns
tDIHD Hold time, DIN valid after SCLK falling edge 10 11 ns
tCSH Pulse duration, CS high 2 2 tCLK
tSCCS Delay time, CS rising edge after final SCLK falling edge 4 4 tCLK
tSDECODE Command decode time 4 4 tCLK
tDISCK2ST Setup time, DAISY_IN valid before SCLK falling edge 10 10 ns
tDISCK2HT Hold time, DAISY_IN valid after SCLK falling edge 10 10 ns

7.7 Switching Characteristics

over operating ambient temperature range, DVDD = 1.7 V to 3.6 V, and load on DOUT = 20 pF || 100 kΩ (unless otherwise noted)
PARAMETER 2.7 V ≤ DVDD ≤ 3.6 V 1.7 V ≤ DVDD ≤ 2.0 V UNIT
MIN MAX MIN MAX
tCSDOD Propagation delay time, CS falling edge to DOUT driven 10 20 ns
tDOST Propagation delay time, SCLK rising edge to valid new DOUT 17 32 ns
tDOHD Hold time, SCLK falling edge to invalid DOUT 10 10 ns
tCSDOZ Propagation delay time, CS rising edge to DOUT high impedance 10 20 ns
ADS131E04 ADS131E06 ADS131E08 tim_serial_bas561.gif

NOTE:

SPI settings are CPOL = 0 and CPHA = 1.
Figure 1. Serial Interface Timing
ADS131E04 ADS131E06 ADS131E08 tim_daisy_chain_bas561.gif
1. n = Number of channels × resolution + 24 bits. Number of channels is 8; resolution is 24-bit.
Figure 2. Daisy-Chain Interface Timing

7.8 Typical Characteristics

all plots are at TA = 25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.4 V, VREFN = AVSS, external clock = 2.048 MHz, data rate = 8 kSPS, and gain = 1, unless otherwise noted.
ADS131E04 ADS131E06 ADS131E08 G003_SBAS561.png
Figure 3. Input-Referred Noise
ADS131E04 ADS131E06 ADS131E08 G005_SBAS561.png
Figure 5. CMRR vs Frequency
ADS131E04 ADS131E06 ADS131E08 G007_SBAS561.png
Figure 7. PSRR vs Frequency
ADS131E04 ADS131E06 ADS131E08 G009_SBAS561.png
Figure 9. INL vs Temperature
ADS131E04 ADS131E06 ADS131E08 G011_SBAS561.png
Figure 11. FFT Plot
ADS131E04 ADS131E06 ADS131E08 G013_SBAS561.png
Figure 13. Offset Drift vs PGA Gain
ADS131E04 ADS131E06 ADS131E08 C001_SBAS561.png
Figure 15. Internal VREF vs Temperature
ADS131E04 ADS131E06 ADS131E08 G004_SBAS561.png
Figure 4. Noise Histogram
ADS131E04 ADS131E06 ADS131E08 G006_SBAS561.png
Figure 6. THD vs Frequency
ADS131E04 ADS131E06 ADS131E08 G008_SBAS561.png
Figure 8. INL vs PGA Gain
ADS131E04 ADS131E06 ADS131E08 G010_SBAS561.png
Figure 10. THD FFT Plot
ADS131E04 ADS131E06 ADS131E08 G012_SBAS561.png
Figure 12. Offset vs PGA Gain (Absolute Value)
ADS131E04 ADS131E06 ADS131E08 G014_SBAS561.png
Figure 14. ADS131E08 Channel Power