SBAS950B October   2019  – February 2021 ADS131M08

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Measurements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input ESD Protection Circuitry
      2. 8.3.2  Input Multiplexer
      3. 8.3.3  Programmable Gain Amplifier (PGA)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Clocking and Power Modes
      6. 8.3.6  ΔΣ Modulator
      7. 8.3.7  Digital Filter
        1. 8.3.7.1 Digital Filter Implementation
          1. 8.3.7.1.1 Fast-Settling Filter
          2. 8.3.7.1.2 SINC3 and SINC3 + SINC1 Filter
        2. 8.3.7.2 Digital Filter Characteristic
      8. 8.3.8  DC Block Filter
      9. 8.3.9  Internal Test Signals
      10. 8.3.10 Channel Phase Calibration
      11. 8.3.11 Calibration Registers
      12. 8.3.12 Communication Cyclic Redundancy Check (CRC)
      13. 8.3.13 Register Map CRC
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset
        2. 8.4.1.2 SYNC/RESET Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Fast Startup Behavior
      3. 8.4.3 Conversion Modes
        1. 8.4.3.1 Continuous-Conversion Mode
        2. 8.4.3.2 Global-Chop Mode
      4. 8.4.4 Power Modes
      5. 8.4.5 Standby Mode
      6. 8.4.6 Current-Detect Mode
    5. 8.5 Programming
      1. 8.5.1 Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Data Clock (SCLK)
        3. 8.5.1.3  Serial Data Input (DIN)
        4. 8.5.1.4  Serial Data Output (DOUT)
        5. 8.5.1.5  Data Ready (DRDY)
        6. 8.5.1.6  Conversion Synchronization or System Reset (SYNC/RESET)
        7. 8.5.1.7  SPI Communication Frames
        8. 8.5.1.8  SPI Communication Words
        9. 8.5.1.9  ADC Conversion Data
          1. 8.5.1.9.1 Collecting Data for the First Time or After a Pause in Data Collection
        10. 8.5.1.10 Commands
          1. 8.5.1.10.1 NULL (0000 0000 0000 0000)
          2. 8.5.1.10.2 RESET (0000 0000 0001 0001)
          3. 8.5.1.10.3 STANDBY (0000 0000 0010 0010)
          4. 8.5.1.10.4 WAKEUP (0000 0000 0011 0011)
          5. 8.5.1.10.5 LOCK (0000 0101 0101 0101)
          6. 8.5.1.10.6 UNLOCK (0000 0110 0110 0110)
          7. 8.5.1.10.7 RREG (101a aaaa annn nnnn)
            1. 8.5.1.10.7.1 Reading a Single Register
            2. 8.5.1.10.7.2 Reading Multiple Registers
          8. 8.5.1.10.8 WREG (011a aaaa annn nnnn)
        11. 8.5.1.11 Short SPI Frames
      2. 8.5.2 Synchronization
    6. 8.6 Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Antialiasing
      3. 9.1.3 Minimum Interface Connections
      4. 9.1.4 Power Metrology Applications
      5. 9.1.5 Multiple Device Configuration
      6. 9.1.6 Code Example
      7. 9.1.7 Troubleshooting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Voltage Measurement Front-End
        2. 9.2.2.2 Current Measurement Front-End
        3. 9.2.2.3 ADC Setup
        4. 9.2.2.4 Calibration
        5. 9.2.2.5 Formulae
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 CAP Pin Behavior
    2. 10.2 Power-Supply Sequencing
    3. 10.3 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-20210129-CA0I-BPZP-RWM6-J91QZ8JX2FR4-low.gif Figure 5-1 PBS Package,32-Pin TQFP,Top View
GUID-20210127-CA0I-SVFD-28MF-Z1GWCLJD71WV-low.gif Figure 5-2 RSN Package,32-Pin WQFN,Top View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION(1)
NAME NO.
WQFN TQFP
AGND 13, 28 13, 28 Supply Analog ground
AIN0N 30 30 Analog input Negative analog input 0
AIN0P 29 29 Analog input Positive analog input 0
AIN1N 31 31 Analog input Negative analog input 1
AIN1P 32 32 Analog input Positive analog input 1
AIN2N 2 2 Analog input Negative analog input 2
AIN2P 1 1 Analog input Positive analog input 2
AIN3N 3 3 Analog input Negative analog input 3
AIN3P 4 4 Analog input Positive analog input 3
AIN4N 6 6 Analog input Negative analog input 4
AIN4P 5 5 Analog input Positive analog input 4
AIN5N 7 7 Analog input Negative analog input 5
AIN5P 8 8 Analog input Positive analog input 5
AIN6N 10 10 Analog input Negative analog input 6
AIN6P 9 9 Analog input Positive analog input 6
AIN7N 11 11 Analog input Negative analog input 7
AIN7P 12 12 Analog input Positive analog input 7
AVDD 15 15 Supply Analog supply. Connect a 1-µF capacitor to AGND.
CAP 24 24 Analog output Digital low-dropout (LDO) regulator output.
Connect a 220-nF capacitor to DGND.
CS 17 17 Digital input Chip select; active low
DGND 25 25 Supply Digital ground
DIN 21 21 Digital input Serial data input
DOUT 20 20 Digital output Serial data output
DRDY 18 18 Digital output Data ready; active low
DVDD 26 26 Supply Digital I/O supply. Connect a 1-µF capacitor to DGND.
NC 27 27 — Leave unconnected or connect to AGND
REFIN 14 14 Analog input External reference voltage input. (2)
SCLK 19 19 Digital input Serial data clock
SYNC/RESET 16 16 Digital input Conversion synchronization or system reset; active low
XTAL1/CLKIN 23 23 Digital input Master clock input, or crystal oscillator input
XTAL2 22 22 Digital output Crystal oscillator excitation(3)
Thermal pad — — Thermal pad; connect to AGND
(1) See the Section 9.1.1 section for details on how to connect unused pins.
(2) Do not place any capacitance on REFIN if the current-detect mode is used.
(3) See the Section 8.3.5 section for more information regarding synchronization and how to implement the clocking scheme for optimized device performance.