SBAS520C February   2011  – June 2017 ADS4122 , ADS4125 , ADS4142 , ADS4145

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Family Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ADS412x
    6. 7.6  Electrical Characteristics: ADS414x
    7. 7.7  Electrical Characteristics: General
    8. 7.8  Digital Characteristics
    9. 7.9  Timing Requirements: LVDS and CMOS Modes
    10. 7.10 Serial Interface Timing Characteristics
    11. 7.11 Reset Timing Requirements
    12. 7.12 Timing Characteristics at Lower Sampling Frequencies
    13. 7.13 Typical Characteristics: ADS4122
    14. 7.14 Typical Characteristics: ADS4125
    15. 7.15 Typical Characteristics: ADS4142
    16. 7.16 Typical Characteristics: ADS4145
    17. 7.17 Typical Characteristics: Common
    18. 7.18 Typical Characteristics: Contour
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Digital Functions and Low-Latency Mode
      2. 8.3.2 Gain for SFDR, SNR Trade-Off
      3. 8.3.3 Offset Correction
      4. 8.3.4 Power-Down
        1. 8.3.4.1 Power-Down Global
        2. 8.3.4.2 Standby
        3. 8.3.4.3 Output Buffer Disable
        4. 8.3.4.4 Input Clock Stop
      5. 8.3.5 Output Data Format
    4. 8.4 Device Functional Modes
      1. 8.4.1 Digital Output Information
        1. 8.4.1.1 Output Interface
        2. 8.4.1.2 DDR LVDS Outputs
        3. 8.4.1.3 LVDS Output Data and Clock Buffers
        4. 8.4.1.4 Parallel CMOS Interface
        5. 8.4.1.5 CMOS Interface Power Dissipation
    5. 8.5 Programming
      1. 8.5.1 Device Configuration
      2. 8.5.2 Serial Interface
        1. 8.5.2.1 Register Initialization
      3. 8.5.3 Serial Register Readout
    6. 8.6 Register Maps
      1. 8.6.1 Serial Register Map
      2. 8.6.2 Description of Serial Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Analog Input
        1. 9.1.1.1 Drive Circuit Requirements
        2. 9.1.1.2 Driving Circuit
        3. 9.1.1.3 Input Common-Mode
      2. 9.1.2 Clock Input
      3. 9.1.3 Input Overvoltage Indication (OVR Pin)
      4. 9.1.4 Using the ADS41xx at Low Sampling Rates
        1. 9.1.4.1 ADS412x (12-Bit Device)
        2. 9.1.4.2 ADS414x (14-Bit Device)
        3. 9.1.4.3 Power Consumption at Low Sampling Rates
        4. 9.1.4.4 Output Timing at Low Sampling Rates
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Analog Input
        2. 9.2.2.2 Clock Driver
        3. 9.2.2.3 Digital Interface
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Sharing DRVDD and AVDD Supplies
    2. 10.2 Using DC-DC Power Supplies
    3. 10.3 Power Supply Bypassing
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Grounding
      2. 11.1.2 Supply Decoupling
      3. 11.1.3 Exposed Pad
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

ADS412x RGZ Package
48-Pin VQFN With Exposed Thermal Pad
LVDS Mode - Top View
ADS4122 ADS4125 ADS4142 ADS4145 po_lvds_412x_bas483.gif
ADS414x RGZ Package
48-Pin VQFN With Exposed Thermal Pad
LVDS Mode - Top View
ADS4122 ADS4125 ADS4142 ADS4145 po_lvds_414x_bas483.gif

NOINDENT:

The thermal pad is connected to DRGND.

Pin Functions: LVDS Mode

PIN I/O DESCRIPTION
NAME ADS412x ADS414x
AGND 9, 12, 14, 17, 19, 25 9, 12, 14, 17, 19, 25 I Analog ground
AVDD 8, 18, 20, 22, 24, 26 8, 18, 20, 22, 24, 26 I 1.8-V analog power supply
CLKM 11 11 I Differential clock input, complement
CLKP 10 10 I Differential clock input, true
CLKOUTM 4 4 O Differential output clock, complement
CLKOUTP 5 5 O Differential output clock, true
D0_D1_M 37 33 O Differential output data D0 and D1 multiplexed, complement
D0_D1_P 38 34 O Differential output data D0 and D1 multiplexed, true
D2_D3_M 39 37 O Differential output data D2 and D3 multiplexed, complement
D2_D3_P 40 38 O Differential output data D2 and D3 multiplexed, true
D4_D5_M 41 39 O Differential output data D4 and D5 multiplexed, complement
D4_D5_P 42 40 O Differential output data D4 and D5 multiplexed, true
D6_D7_M 43 41 O Differential output data D6 and D7 multiplexed, complement
D6_D7_P 44 42 O Differential output data D6 and D7 multiplexed, true
D8_D9_M 45 43 O Differential output data D8 and D9 multiplexed, complement
D8_D9_P 46 44 O Differential output data D8 and D9 multiplexed, true
D10_D11_M 47 45 O Differential output data D10 and D11 multiplexed, complement
D10_D11_P 48 46 O Differential output data D10 and D11 multiplexed, true
D12_D13_M — 47 O Differential output data D12 and D13 multiplexed, complement
D12_D13_P — 48 O Differential output data D12 and D13 multiplexed, true
DFS 6 6 I Data format select input. This pin sets the DATA FORMAT (twos complement or offset binary) and the LVDS, CMOS output interface type. See Table 5 for detailed information.
DRGND 1, 36, PAD 1, 36, PAD I Digital and output buffer ground
DRVDD 2, 35 2, 35 I 1.8-V digital and output buffer supply
INM 16 16 I Differential analog input, negative
INP 15 15 I Differential analog input, positive
NC 21, 31, 32, 33, 34 21, 31, 32 – Do not connect
OE 7 7 I Output buffer enable input, active high; this pin has an internal 180-kΩ pullup resistor to DRVDD.
OVR_SDOUT 3 3 O This pin functions as an out-of-range indicator after reset, when register bit
READOUT = 0, and functions as a serial register readout pin when READOUT = 1.
RESERVED 23 23 I Digital control pin, reserved for future use
RESET 30 30 I Serial interface RESET input.
When using the serial interface mode, the internal registers must initialize through hardware RESET by applying a high pulse on this pin or by using the software reset option; see the Serial Interface section.
When RESET is tied high, the internal registers are reset to the default values. In this condition, SEN can be used as an analog control pin.
RESET has an internal 180-kΩ pulldown resistor.
SCLK 29 29 I This pin functions as a serial interface clock input when RESET is low. When RESET is high, SCLK has no function and should be tied to ground. This pin has an internal 180-kΩ pulldown resistor.
SDATA 28 28 I This pin functions as a serial interface data input when RESET is low. When RESET is high, SDATA functions as a STANDBY control pin (see Table 7). This pin has an internal 180-kΩ pulldown resistor.
SEN 27 27 I This pin functions as a serial interface enable input when RESET is low. When RESET is high, SEN has no function and must be tied to AVDD. This pin has an internal 180-kΩ pullup resistor to AVDD.
VCM 13 13 O Outputs the common-mode voltage (0.95 V) that can be used externally to bias the analog input pins.
ADS412x RGZ Package
48-PIN VQFN With Exposed Thermal Pad
CMOS Mode - Top View
ADS4122 ADS4125 ADS4142 ADS4145 po_cmos_412x_bas483.gif
ADS414x RGZ Package
48-PIN VQFN With Exposed Thermal Pad
CMOS Mode - Top View
ADS4122 ADS4125 ADS4142 ADS4145 po_cmos_414x_bas483.gif
The thermal pad is connected to DRGND.

Pin Functions: CMOS Mode

PIN I/O DESCRIPTION
NAME ADS412x ADS414x
AVDD 8, 18, 20, 22, 24, 26 8, 18, 20, 22, 24, 26 I 1.8-V analog power supply
AGND 9, 12, 14, 17, 19, 25 9, 12, 14, 17, 19, 25 I Analog ground
CLKM 11 11 I Differential clock input, complement
CLKP 10 10 I Differential clock input, true
CLKOUT 5 5 O CMOS output clock
D0 37 33 O 12-bit, 14-bit CMOS output data
D1 38 34 O 12-bit, 14-bit CMOS output data
D2 39 37 O 12-bit, 14-bit CMOS output data
D3 40 38 O 12-bit, 14-bit CMOS output data
D4 41 39 O 12-bit, 14-bit CMOS output data
D5 42 40 O 12-bit, 14-bit CMOS output data
D6 43 41 O 12-bit, 14-bit CMOS output data
D7 44 42 O 12-bit, 14-bit CMOS output data
D8 45 43 O 12-bit, 14-bit CMOS output data
D9 46 44 O 12-bit, 14-bit CMOS output data
D10 47 45 O 12-bit, 14-bit CMOS output data
D11 48 46 O 12-bit, 14-bit CMOS output data
D12 — 47 O 12-bit, 14-bit CMOS output data
D13 — 48 O 12-bit, 14-bit CMOS output data
DFS 6 6 I Data format select input. This pin sets the DATA FORMAT (twos complement or offset binary) and the LVDS, CMOS output interface type. See Table 5 for detailed information.
DRGND 1, 36, PAD 1, 36, PAD I Digital and output buffer ground
DRVDD 2, 35 2, 35 I 1.8-V digital and output buffer supply
INM 16 16 I Differential analog input, negative
INP 15 15 I Differential analog input, positive
NC 21, 31, 32, 33, 34 21, 31, 32 – Do not connect
OE 7 7 I Output buffer enable input, active high; this pin has an internal 180-kΩ pullup resistor to DRVDD.
OVR_SDOUT 3 3 O This pin functions as an out-of-range indicator after reset, when register bit
READOUT = 0, and functions as a serial register readout pin when READOUT = 1.
RESERVED 23 23 I Digital control pin, reserved for future use
RESET 30 30 I Serial interface RESET input.
When using the serial interface mode, the internal registers must initialize through hardware RESET by applying a high pulse on this pin or by using the software reset option; see the Serial Interface section.
When RESET is tied high, the internal registers are reset to the default values. In this condition, SEN can be used as an analog control pin.
RESET has an internal 180-kΩ pulldown resistor.
SCLK 29 29 I This pin functions as a serial interface clock input when RESET is low. When RESET is high, SCLK has no function and must be tied to ground. This pin has an internal 180-kΩ pulldown resistor.
SDATA 28 28 I This pin functions as a serial interface data input when RESET is low. When RESET is high, SDATA functions as a STANDBY control pin (see Table 7). This pin has an internal 180-kΩ pulldown resistor.
SEN 27 27 I This pin functions as a serial interface enable input when RESET is low. When RESET is high, SEN has no function and must be tied to AVDD. This pin has an internal 180-kΩ pullup resistor to AVDD.
UNUSED 4 4 – Unused pin in CMOS mode
VCM 13 13 O Outputs the common-mode voltage (0.95 V) that can be used externally to bias the analog input pins.