8.3.1 Test Pattern Output

The ADS5401 can be configured to output different test patterns that can be used to verify the digital interface is connected and working properly. To enable test pattern mode, high performance mode 1 has to be disabled first through a SPI register write. Then different test patterns can be selected by configuring registers x3C, x3D and x3E. All three registers must be configured for the test pattern to work properly.

First set HP1 = 0 (Addr 0x01, D01).

For normal operation, set HP1 = 1 (Addr 0x01, D01) and 0x3C, 0x3D, 0x3E all to 0.

8.3.2 Clock Input

The ADS5401 clock input can be driven differentially with a sine wave, LVPECL or LVDS source with little or no difference in performance. The common-mode voltage of the clock input is set to 0.9 V using internal 2-kΩ resistors. This allows for AC coupling of the clock inputs. The termination resistors should be placed as close as possible to the clock inputs in order to minimize signal reflections and jitter degradation.

Figure 36. Recommended Differential Clock Driving Circuit

8.3.3 Analog Inputs

The ADS5401 analog signal input is designed to be driven differentially. The analog input pins have internal analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high impedance input across a very wide frequency range to the external driving source which enables great flexibility in the external analog filter design as well as excellent 50-Ω matching for RF applications. The buffer also helps to isolate the external driving circuit from the internal switching currents of the sampling circuit which results in a more constant SFDR performance across input frequencies.

The common-mode voltage of the signal input is internally biased to 1.9 V using 500-Ω resistors which allows for AC coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.25 V) and (VCM – 0.25 V), resulting in a 1.0-Vpp (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 1.2 GHz.

Figure 37. Equivalent Analog Input Circuit

8.3.4 Overrange Indication

The ADS5401 provides a fast overrange indication on the OVRA pins. The fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and it gets presented after just 12 clock cycles enabling a quicker reaction to an overrange event. The OVR threshold can be configured using SPI register writes.

The input voltage level at which the overload is detected is referred to as the threshold and is programmable using the overrange threshold bits. The threshold at which fast OVR is triggered is (full-scale × [the decimal value of the FAST OVR THRESH bits] /16). After reset, the default value of the overrange threshold is set to 15 (decimal) which corresponds to a threshold of 0.56 dB below full scale (20 × log(15/16)).

Figure 38. OVR Detection Threshold

8.3.5 Interleaving Correction

The two data converter channel consists of two interleaved ADCs each operating at half of the ADC sampling rate but 180º out of phase from each other. The front end track and hold circuitry is operating at the full ADC sampling rate which minimizes the timing mismatch between the two interleaved ADCs. In addition the ADS5401 is equipped with internal interleaving correction logic that can be enabled through SPI register write.

Figure 39. Interleaving Correction Circuit

The interleaving operation creates 2 distinct and interleaving products:

• Fs/2 – Fin: this spur is created by gain timing mismatch between the ADCs. Because internally the front end track and hold is operated at the full sampling rate, this component is greatly improved and mostly dependent on gain mismatch.
• Fs/2 Spur: due to offset mismatch between ADCs.

Figure 40. Interleaving Spur at Fs/2 due to Offset Mismatch

The auto correction loop can be enabled through SPI register write in address 0x01 and resetting the correction circuit in address 0x03. By default it is disabled for lowest possible power consumption.

The auto correction function yields best performance for input frequencies below 250 MHz.

8.3.6 Decimation Filter

There is an optional digital decimation filter in the data path as shown in Figure 41. The filter can be programmed as a lowpass or a highpass filter and the normalized frequency response of both filters is shown in Figure 42.

Figure 41. 2x Decimation Filter

The decimation filter response has a 0.1-dB pass band ripple with approximately 41% pass-band bandwidth. The stop-band attenuation is approximately 40 dB.

Figure 42. Decimation Filter Response

Figure 43. Decimation Filter Response

8.3.7 Multi Device Synchronization

The ADS5401 simplifies the synchronization of data from multiple ADCs in one common receiver. Upon receiving the initial SYNC input signal, the ADS5401 resets all the internal clocks and digital logic while also starting a SYNCOUT signal which operates on a 5-bit counter (32 clock cycles). Therefore by providing a common SYNC signal to multiple ADCs their output data can be synchronized as the SYNCOUT signal marks a specific sample with the same latency in all ADCs. The SYNCOUT signal then can be used in the receiving device to synchronize the FIFO pointers across the different input data streams. Thus the output data of multiple ADCs can be aligned properly even if there are different trace lengths between the different ADCs. By default ADS5401 is not configured for multi device synchronization. The ADC can be configured by setting the SYNCOUT enable bit (D2 config1) to 1 on all the ADCs.

Figure 44. Multiple ADC Synchronization

The SYNC input signal should be a one time pulse to trigger the periodic 5-bit counter for SYNCOUT or a periodic signal repeating every 32 CLKIN clock cycles. It gets registered on the rising edge of the ADC input clock (CLKIN). Upon registering the initial rising edge of the SYNC signal, the internal clocks and logic get reset which results in invalid output data for 36 samples (1 complete sync cycle and 4 additional samples). The SYNCOUT signal starts with the next output clock (DACLK) rising edge and operates on a 5-bit counter. If a SYNCIN rising edge gets registered at a new position, the counter gets reset and SYNCOUT starts from the new position.

Because the ADS5401 output interface operates with a DDR clock, the synchronization can happen on the rising edge or falling edge sample. Synchronization on the falling edge sample will result in a half cycle clock stretch of DACLK. For convenience the SYNCOUT signal is available on the ChA output LVDS bus. When using decimation the SYNCOUT signal still operates on 32 clock cycles of CLKIN but since the output data is decimated by 2, only the first 18 samples should be discarded.

Figure 45. Multiple Device Synchronization Timing Diagram

8.4.1 Power-Down Modes

The ADS5401 can be configured through SPI write (address x37) to a standby, light or deep sleep power mode which is controlled by the ENABLE pin. The sleep modes are active when the ENABLE pin goes low. Different internal functions stay powered up which results in different power consumption and wake up time between the two sleep modes.

8.5.1 Device Initialization

After power up, TI recommends using the device through a hardware reset by applying a logic low pulse on the SRESETb pin (of width greater than 20ns), as shown in Figure 2. This resets all internal digital blocks (including SPI registers) to their default condition.

Recommended Device Initialization Sequence:

1. Power up
2. Reset ADS5401 using hardware reset.
3. Apply clock and input signal.
4. Set register 0x01 bit D15 to 1 (ChA Corr EN) to enable gain/offset correction circuit and other desired registers.
5. Set register 0x03 bit D14 to 1 (Start Auto Corr ChA). This clears and resets the accumulator values in the DC and gain correction loop.
6. Set register 0x03 bit D14 to 0 (Start Auto Corr ChA). This starts the DC and gain auto-correction loop.

8.5.2 Serial Register Write

The internal register of the ADS5401 can be programmed following these steps:

1. Drive SDENB pin low
2. Set the R/W bit to 0 (bit A7 of the 8 bit address)
3. Initiate a serial interface cycle specifying the address of the register (A6 to A0) whose content has to be written
4. Write 16bit data which is latched on the rising edge of SCLK

Figure 46. Serial Register Write Timing Diagram

8.5.3 Serial Register Readout

The device includes a mode where the contents of the internal registers can be read back using the SDO/SDIO pins. This read-back mode may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC.

1. Drive SDENB pin low
2. Set the RW bit (A7) to 1. This setting disables any further writes to the registers
3. Initiate a serial interface cycle specifying the address of the register (A6 to A0) whose content has to be read.
4. The device outputs the contents (D15 to D0) of the selected register on the SDO/SDIO pin
5. The external controller can latch the contents at the SCLK rising edge.
6. To enable register writes, reset the RW register bit to 0.

Figure 47. Serial Register Read Timing Diagram

Table 4. Serial Register Map⁽¹⁾

8.6.1 Register Name: Config0 - Address: 0×00, Default = 0×00

8.6.2 Register Name: Config1 - Address: 0×01, Default = 0×00

8.6.3 Register Name: Config2 - Address: 0×02, Default = 0×780

Figure 51. OVR Detection Threshold

8.6.4 Register Name: 3 - Address: 0x03

8.6.5 Register Name: E - Address: 0x0E

8.6.6 Register Name: F - Address: 0x0F

8.6.7 Register Name: 2B - Address: 0x2B

8.6.8 Register Name: 2C - Address: 0x2C

8.6.9 Register Name: 37 - Address: 0x37

8.6.10 Register Name: 38 - Address: 0x38

8.6.11 Register Name: 3A - Address: 0x3A

8.6.12 Register Name: 66 - Address: 0x66