SBAS706D April 2015 – April 2019 ADS54J60
PRODUCTION DATA.
Figure 84 shows a conceptual diagram of the serial registers.
The ADS54J60 contains two main SPI banks. The analog SPI bank gives access to the ADC analog blocks and the digital SPI bank controls the interleaving engine and anything related to the JESD204B serial interface. The analog SPI bank is divided into two pages (master and ADC) and the digital SPI bank is divided into three pages (main digital, JESD digital, and JESD analog). Table 15 lists a register map for the ADS54J60.
REGISTER ADDRESS | REGISTER DATA | |||||||
---|---|---|---|---|---|---|---|---|
A[11:0] (Hex) | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GENERAL REGISTERS | ||||||||
0 | RESET | 0 | 0 | 0 | 0 | 0 | 0 | RESET |
1 | JESD BANK PAGE SEL1[7:0] | |||||||
2 | JESD BANK PAGE SEL1[15:8] | |||||||
3 | JESD BANK PAGE SEL[7:0] | |||||||
4 | JESD BANK PAGE SEL[15:8] | |||||||
5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DISABLE BROADCAST |
11 | ANALOG BANK PAGE SEL | |||||||
MASTER PAGE (ANALOG BANK PAGE SEL = 80h) | ||||||||
20 | PDN ADC CHA | PDN ADC CHB | ||||||
21 | PDN BUFFER CHB | PDN BUFFER CHA | 0 | 0 | 0 | 0 | ||
23 | PDN ADC CHA | PDN ADC CHB | ||||||
24 | PDN BUFFER CHB | PDN BUFFER CHA | 0 | 0 | 0 | 0 | ||
26 | GLOBAL PDN | OVERRIDE PDN PIN | PDN MASK SEL | 0 | 0 | 0 | 0 | 0 |
4F | 0 | 0 | 0 | 0 | 0 | 0 | 0 | EN INPUT DC COUPLING |
53 | 0 | 0 | 0 | 0 | 0 | 0 | EN SYSREF DC COUPLING | MANUAL SYSREF |
54 | ENABLE MANUAL SYSREF | 0 | MASK SYSREF | 0 | 0 | 0 | 0 | |
55 | 0 | 0 | 0 | PDN MASK | 0 | 0 | 0 | 0 |
59 | FOVR CHB | 0 | ALWAYS WRITE 1 | 0 | 0 | 0 | 0 | 0 |
ADC PAGE (ANALOG BANK PAGE SEL = 0Fh) | ||||||||
5F | FOVR THRESHOLD PROG | |||||||
MAIN DIGITAL PAGE (JESD BANK PAGE SEL = 6800h) | ||||||||
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | PULSE RESET |
41 | 0 | 0 | DECFIL MODE[3] | DECFIL EN | 0 | DECFIL MODE[2:0] | ||
42 | 0 | 0 | 0 | 0 | 0 | NYQUIST ZONE | ||
43 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | FORMAT SEL |
44 | 0 | DIGITAL GAIN | ||||||
4B | 0 | 0 | FORMAT EN | 0 | 0 | 0 | 0 | 0 |
4D | 0 | 0 | 0 | 0 | DEC MODE EN | 0 | 0 | 0 |
4E | CTRL NYQUIST | 0 | IMPROVE IL PERF | 0 | 0 | 0 | 0 | 0 |
52 | BUS_
REORDER EN1 |
0 | 0 | 0 | 0 | 0 | 0 | DIG GAIN EN |
72 | 0 | 0 | 0 | 0 | BUS_
REORDER EN2 |
0 | 0 | 0 |
AB | 0 | 0 | 0 | 0 | 0 | 0 | 0 | LSB SEL EN |
AD | 0 | 0 | 0 | 0 | 0 | 0 | LSB SELECT | |
F7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DIG RESET |
JESD DIGITAL PAGE (JESD BANK PAGE SEL = 6900h) | ||||||||
0 | CTRL K | 0 | 0 | TESTMODE EN | FLIP ADC DATA | LANE ALIGN | FRAME ALIGN | TX LINK DIS |
1 | SYNC REG | SYNC REG EN | JESD FILTER | JESD MODE | ||||
2 | LINK LAYER TESTMODE | LINK LAYER RPAT | LMFC MASK RESET | 0 | 0 | 0 | ||
3 | FORCE LMFC COUNT | LMFC COUNT INIT | RELEASE ILANE SEQ | |||||
5 | SCRAMBLE EN | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
6 | 0 | 0 | 0 | FRAMES PER MULTI FRAME (K) | ||||
7 | 0 | 0 | 0 | 0 | SUBCLASS | 0 | 0 | 0 |
16 | 1 | 0 | 0 | LANE SHARE | 0 | 0 | 0 | 0 |
31 | DA_BUS_REORDER[7:0] | |||||||
32 | DB_BUS_REORDER[7:0] | |||||||
JESD ANALOG PAGE (JESD BANK PAGE SEL = 6A00h) | ||||||||
12 | SEL EMP LANE 1 | ALWAYS WRITE 1 | 0 | |||||
13 | SEL EMP LANE 0 | 0 | 0 | |||||
14 | SEL EMP LANE 2 | 0 | 0 | |||||
15 | SEL EMP LANE 3 | 0 | 0 | |||||
16 | 0 | 0 | 0 | 0 | 0 | 0 | JESD PLL MODE | |
17 | 0 | PLL RESET | LANE PDN 1 | 0 | LANE PDN 0 | 0 | 0 | 0 |
1A | 0 | 0 | 0 | 0 | 0 | 0 | FOVR CHA | 0 |
1B | JESD SWING | 0 | FOVR CHA EN | 0 | 0 | 0 | ||
OFFSET READ PAGE (JESD BANK PAGE SEL = 6100h, JESD BANK PAGE SEL1 = 0000h) | ||||||||
68 | FREEZE CORR | DC OFFSET CORR BW | BYPASS CORR | ALWAYS WRITE 1 | 0 | |||
69 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | EXT CORR EN |
74 | ADC0_CORR_INT_EST[7:0] | |||||||
75 | 0 | 0 | 0 | 0 | 0 | ADC0_CORR_INT_EST[10:8] | ||
76 | ADC1_CORR_INT_EST[7:0] | |||||||
77 | 0 | 0 | 0 | 0 | 0 | ADC1_CORR_INT_EST[10:8] | ||
78 | ADC2_CORR_INT_EST[7:0] | |||||||
79 | 0 | 0 | 0 | 0 | 0 | ADC2_CORR_INT_EST[10:8] | ||
7A | ADC3_CORR_INT_EST[7:0] | |||||||
7B | 0 | 0 | 0 | 0 | 0 | ADC3_CORR_INT_EST[10:8] | ||
OFFSET LOAD PAGE (JESD BANK PAGE SEL = 6100h, JESD BANK PAGE SEL1 = 0500h) | ||||||||
00 | ADC0_LOAD_INT_EST[7:0] | |||||||
01 | 0 | 0 | 0 | 0 | 0 | ADC0_CORR_INT_EST[10:8] | ||
04 | ADC1_LOAD_INT_EST[7:0] | |||||||
05 | 0 | 0 | 0 | 0 | 0 | ADC1_CORR_INT_EST[10:8] | ||
08 | ADC2_LOAD_INT_EST[7:0] | |||||||
09 | 0 | 0 | 0 | 0 | 0 | ADC2_CORR_INT_EST[10:8] | ||
0C | ADC3_LOAD_INT_EST[7:0] | |||||||
0D | 0 | 0 | 0 | 0 | 0 | ADC3_CORR_INT_EST[10:8] |