SLAS600C May 2008 – December 2016 ADS8319
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
- DRC|10
Orderable Information
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)| MIN | MAX | UNIT | |
|---|---|---|---|
| +IN pin voltage | –0.3 | +VA + 0.3 | V |
| +IN pin current | ±130 | mA | |
| –IN pin voltage | –0.3 | 0.3 | V |
| –IN pin current | ±130 | mA | |
| +VA to AGND | –0.3 | 7 | V |
| +VBD to BDGND | –0.3 | 7 | V |
| Digital input voltage to GND | –0.3 | +VBD + 0.3 | V |
| Digital output to GND | –0.3 | +VBD + 0.3 | V |
| Maximum VSSOP reflow temperature(2) | 260 | °C | |
| Maximum VSON reflow temperature(2) | 260 | °C | |
| Operating free-air temperature, TA | –40 | 85 | °C |
| Junction temperature, TJ(MAX) | 150 | °C | |
| Storage temperature, Tstg | –65 | 150 | °C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The device is rated to MSL2 260°C, as per the JSTD-020 specification.
7.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| +VA | Analog power-supply voltage | 4.5 | 5 | 5.5 | V |
| +VBD | Digital I/O-supply voltage | 2.375 | 3.3 | 5.5 | V |
| VREF | Reference voltage | 2.25 | 4.096 | +VA + 0.1 | V |
| TA | Operating temperature | –40 | 85 | °C | |
7.4 Thermal Information
| THERMAL METRIC(1) | ADS8319 | UNIT | ||
|---|---|---|---|---|
| DGS (VSSOP) | DRC (VSON) | |||
| 10 PINS | 10 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 107.5 | 87.2 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 21.8 | 31.1 | °C/W |
| RθJB | Junction-to-board thermal resistance | 24.2 | 25.5 | °C/W |
| ψJT | Junction-to-top characterization parameter | 0.6 | 1 | °C/W |
| ψJB | Junction-to-board characterization parameter | 24.4 | 29.2 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
7.5 Electrical Characteristics
TA = –40°C to 85°C, +VA = 5 V, +VBD = 5 V to 2.375 V, VREF = 4 V, and fSAMPLE = 500 kHz, unless otherwise noted.| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| ANALOG INPUT | |||||||
| Full-scale input span(1) | +IN – (–IN) | 0 | VREF | V | |||
| Operating input | +IN | –0.1 | VREF + 0.1 | V | |||
| –IN | –0.1 | 0.1 | |||||
| Input capacitance | 59 | pF | |||||
| Input leakage current | During acquisition | 1000 | pA | ||||
| SYSTEM PERFORMANCE | |||||||
| Resolution | 16 | Bits | |||||
| No missing codes | 16 | Bits | |||||
| INL | Integral linearity(6) | ADS8319I | –2.5 | ±1.2 | 2.5 | LSB(2) | |
| ADS8319IB | –1.5 | ±1 | 1.5 | ||||
| DNL | Differential linearity | At 16-bit level | ADS8319I | –1 | ±0.65 | 1.5 | LSB |
| ADS8319IB | –1 | ±0.5 | 1 | ||||
| EO | Offset error(3) | –1.5 | ±0.3 | 1.5 | mV | ||
| EG | Gain error | –0.03 | ±0.0045 | 0.03 | %FSR | ||
| CMRR | Common-mode rejection ratio | With common-mode input signal = 200 mVPP at 500 kHz |
78 | dB | |||
| PSRR | Power-supply rejection ratio | At FFF0h output code | 80 | dB | |||
| Transition noise | 0.5 | LSB | |||||
| SAMPLING DYNAMICS | |||||||
| tCONV | Conversion time | +VBD = 5 V | 1400 | ns | |||
| +VBD = 3 V | 1400 | ||||||
| Acquisition time | +VBD = 5 V | 600 | ns | ||||
| +VBD = 3 V | 600 | ||||||
| Maximum throughput rate with or without latency | 0.5 | MHz | |||||
| Aperture delay | 2.5 | ns | |||||
| Aperture jitter, RMS | 6 | ps | |||||
| Step response | Settling to 16-bit accuracy | 600 | ns | ||||
| Overvoltage recovery | Settling to 16-bit accuracy | 600 | ns | ||||
| DYNAMIC CHARACTERISTICS | |||||||
| THD | Total harmonic distortion(4) | VIN 0.4 dB below FS at 1 kHz, VREF = 5 V | –111 | dB | |||
| VIN 0.4 dB below FS at 10 kHz, VREF = 5 V | –106 | ||||||
| VIN 0.4 dB below FS at 100 kHz, VREF = 5 V | –89 | ||||||
| SNR | Signal-to-noise ratio | ADS8319IB, VIN 0.4 dB below FS at 1 kHz, VREF = 5 V |
92 | dB | |||
| VIN 0.4 dB below FS at 1 kHz, VREF = 5 V | 93.9 | ||||||
| VIN 0.4 dB below FS at 10 kHz, VREF = 5 V | 93.6 | ||||||
| VIN 0.4 dB below FS at 100 kHz, VREF = 5 V | 92.2 | ||||||
| SINAD | Signal-to-noise + distortion | VIN 0.4 dB below FS at 1 kHz, VREF = 5 V | 93.8 | dB | |||
| VIN 0.4 dB below FS at 10 kHz, VREF = 5 V | 93.4 | ||||||
| VIN 0.4 dB below FS at 100 kHz, VREF = 5 V | 87.4 | ||||||
| SFDR | Spurious-free dynamic range | VIN 0.4 dB below FS at 1 kHz, VREF = 5 V | 113 | dB | |||
| VIN 0.4 dB below FS at 10 kHz, VREF = 5 V | 107 | ||||||
| VIN 0.4 dB below FS at 100 kHz, VREF = 5 V | 90 | ||||||
| –3-dB small-signal bandwidth | 15 | MHz | |||||
| EXTERNAL REFERENCE INPUT | |||||||
| VREF | Reference input | 2.25 | 4.096 | +VA + 0.1 | V | ||
| Reference input current(5) | During conversion | 250 | µA | ||||
| POWER SUPPLY REQUIREMENTS | |||||||
| Power-supply voltage | +VBD | 2.375 | 3.3 | 5.5 | V | ||
| +VA | 4.5 | 5 | 5.5 | ||||
| Supply current | +VA, 500-kHz sample rate | 3.6 | 4.5 | mA | |||
| PVA | Power dissipation | +VA = 5 V, 500-kHz sample rate | 18 | 22.5 | mW | ||
| IVApd | Device power-down current(7) | +VA = 5 V | 50 | 300 | nA | ||
| LOGIC FAMILY CMOS | |||||||
| VIH | Input HIGH logic level | IIH = 5 µA | +(0.7 × VBD) | +VBD + 0.3 | V | ||
| VIL | Input LOW logic level | IIL = 5 µA | –0.3 | +(0.3 × VBD) | |||
| VOH | Output HIGH logic level | IOH = 2 TTL loads | +VBD – 0.3 | +VBD | |||
| VOL | Output LOW logic level | IOL = 2 TTL loads | 0 | 0.4 | |||
(1) Ideal input span, does not include gain or offset error.
(2) LSB means least significant bit.
(3) Measured relative to actual measured reference.
(4) Calculated on the first nine harmonics of the input frequency.
(5) Can vary by ±20%.
(6) This parameter is endpoint INL, not best fit.
(7) The device automatically enters a power-down state at the end of every conversion and remains in a power-down state during the acquisition phase.
7.6 Timing Requirements: +VBD ≥ 4.5 V
All specifications are typical at –40°C to 85°C, +VA = 5 V, and +VBD ≥ 4.5 V, unless otherwise noted.| REFERENCE FIGURE | MIN | MAX | UNIT | ||
|---|---|---|---|---|---|
| SAMPLING AND CONVERSION RELATED | |||||
| tACQ | Acquisition time | Figure 50, Figure 52, Figure 53, Figure 55 | 600 | ns | |
| tcnv | Conversion time | 1400 | ns | ||
| tcyc | Time between conversions | 2000 | ns | ||
| t1 | Pulse duration, CONVST high | Figure 50, Figure 52 | 10 | ns | |
| t6 | Pulse duration, CONVST low | Figure 53, Figure 55, Figure 58 | 20 | ns | |
| I/O RELATED | |||||
| tclk | SCLK period | Figure 50, Figure 52, Figure 53, Figure 55, Figure 58, Figure 60 | 20 | ns | |
| tclkl | SCLK low time | 9 | ns | ||
| tclkh | SCLK high time | 9 | ns | ||
| t2 | SCLK falling edge to data remains valid | 5 | ns | ||
| t3 | SCLK falling edge to next data valid delay | 16 | ns | ||
| ten | Enable time, CONVST or SDI low to MSB valid | Figure 50, Figure 53 | 15 | ns | |
| tdis | Disable time, CONVST or SDI high or last SCLK falling edge to SDO 3-state (CS mode) | Figure 50, Figure 52, Figure 53, Figure 55 | 12 | ns | |
| t4 | Setup time, SDI valid to CONVST rising edge | Figure 53, Figure 55 | 5 | ns | |
| t5 | Hold time, SDI valid from CONVST rising edge | 5 | ns | ||
| t7 | Setup time, SCLK valid to CONVST rising edge | Figure 58 | 5 | ns | |
| t8 | Hold time, SCLK valid from CONVST rising edge | 5 | ns | ||
7.7 Timing Requirements: 4.5 V > +VBD ≥ 2.375 V
All specifications are typical at –40°C to 85°C, +VA = 5 V, and +4.5 V > +VBD ≥ 2.375 V, unless otherwise noted.| REFERENCE FIGURE | MIN | MAX | UNIT | ||
|---|---|---|---|---|---|
| SAMPLING AND CONVERSION RELATED | |||||
| tACQ | Acquisition time | Figure 50, Figure 52, Figure 53, Figure 55 | 600 | ns | |
| tcnv | Conversion time | 1400 | ns | ||
| tcyc | Time between conversions | 2000 | ns | ||
| t1 | Pulse width CONVST high | Figure 50, Figure 52 | 10 | ns | |
| t6 | Pulse width CONVST low | Figure 53, Figure 55, Figure 58 | 20 | ns | |
| I/O RELATED | |||||
| tclk | SCLK period | Figure 50, Figure 52, Figure 53, Figure 55, Figure 58, Figure 60 | 30 | ns | |
| tclkl | SCLK low time | 13 | ns | ||
| tclkh | SCLK high time | 13 | ns | ||
| t2 | SCLK falling edge to data remains valid | 5 | ns | ||
| t3 | SCLK falling edge to next data valid delay | 24 | ns | ||
| ten | CONVST or SDI low to MSB valid | Figure 50, Figure 53 | 22 | ns | |
| tdis | CONVST or SDI high or last SCLK falling edge to SDO 3-state (CS mode) | Figure 50, Figure 52, Figure 53, Figure 55 | 15 | ns | |
| t4 | SDI valid setup time to CONVST rising edge | Figure 53, Figure 55 | 5 | ns | |
| t5 | SDI valid hold time from CONVST rising edge | 5 | ns | ||
| t7 | SCLK valid setup time to CONVST rising edge | Figure 58 | 5 | ns | |
| t8 | SCLK valid hold time from CONVST rising edge | 5 | ns | ||
Figure 1. Load Circuit for Digital Interface Timing
Figure 2. Voltage Levels for Timing
7.8 Typical Characteristics
Figure 3. Offset Error vs Supply Voltage
Figure 5. Offset Error vs Reference Voltage
Figure 7. Offset Error vs Free-Air Temperature
Figure 9. Gain Error Drift Histogram
Figure 11. Differential Nonlinearity vs Supply Voltage
Figure 13. Differential Nonlinearity vs Reference Voltage
Figure 15. Differential Nonlinearity vs Free-Air Temperature
Figure 17. Effective Number of Bits vs Supply Voltage
Figure 19. Effective Number of Bits vs Free-Air Temperature
Figure 21. Signal-to-Noise + Distortion vs Supply Voltage
Figure 23. Total Harmonic Distortion vs Supply Voltage
Figure 25. Signal-to-Noise + Distortion vs Reference Voltage
Figure 27. Total Harmonic Distortion vs Reference Voltage
Figure 29. Signal-to-Noise + Distortionvs Free-Air Temperature
Figure 31. Total Harmonic Distortionvs Free-Air Temperature
Figure 33. Total Harmonic Distortionvs Signal Input Frequency
Figure 35. Total Harmonic Distortion vs Source Resistance
Figure 37. Supply Current vs Free-Air Temperature
Figure 39. Power Dissipation vs Sampling Frequency
Figure 41. Power-Down Current vs Free-Air Temperature
Figure 43. INL
Figure 4. Gain Error vs Supply Voltage
Figure 6. Gain Error vs Reference Voltage
Figure 8. Gain Error vs Free-Air Temperature
Figure 10. Offset Error Drift Histogram
Figure 12. Integral Nonlinearity vs Supply Voltage
Figure 14. Integral Nonlinearity vs Reference Voltage
Figure 16. Integral Nonlinearity vs Free-Air Temperature
Figure 18. Effective Number of Bits vs Reference Voltage
Figure 20. Spurious-Free Dynamic Range vs Supply Voltage
Figure 22. Signal-to-Noise Ratio vs Supply Voltage
Figure 24. Spurious-Free Dynamic Rangevs Reference Voltage
Figure 26. Signal-to-Noise Ratio vs Reference Voltage
Figure 28. Spurious-Free Dynamic Rangevs Free-Air Temperature
Figure 30. Signal-to-Noise Ratio vs Free-Air Temperature
Figure 32. Signal-to-Noise + Distortionvs Signal Input Frequency
Figure 34. DC Histogram of ADC Close to Center Code
Figure 36. Supply Current vs Supply Voltage
Figure 38. Supply Current vs Sampling Frequency
Figure 40. Power-Down Current vs Supply Voltage
Figure 44. FFT