SBASAY5 June   2024 ADS8681W

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Input Structure
      2. 6.3.2 Analog Input Impedance
      3. 6.3.3 Input Protection Circuit
      4. 6.3.4 Programmable Gain Amplifier (PGA)
      5. 6.3.5 Second-Order, Low-Pass Filter (LPF)
      6. 6.3.6 ADC Driver
      7. 6.3.7 Reference
        1. 6.3.7.1 Internal Reference
        2. 6.3.7.2 External Reference
      8. 6.3.8 ADC Transfer Function
      9. 6.3.9 Alarm Features
        1. 6.3.9.1 Input Alarm
        2. 6.3.9.2 AVDD Alarm
    4. 6.4 Device Functional Modes
      1. 6.4.1 Host-to-Device Connection Topologies
        1. 6.4.1.1 Single Device: All multiSPI Options
        2. 6.4.1.2 Single Device: Standard SPI Interface
        3. 6.4.1.3 Multiple Devices: Daisy-Chain Topology
      2. 6.4.2 Device Operational Modes
        1. 6.4.2.1 RESET State
        2. 6.4.2.2 ACQ State
        3. 6.4.2.3 CONV State
    5. 6.5 Programming
      1. 6.5.1 Data Transfer Frame
      2. 6.5.2 Input Command Word and Register Write Operation
      3. 6.5.3 Output Data Word
      4. 6.5.4 Data Transfer Protocols
        1. 6.5.4.1 Protocols for Configuring the Device
        2. 6.5.4.2 Protocols for Reading From the Device
          1. 6.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols With a Single SDO-x
          2. 6.5.4.2.2 Legacy, SPI-Compatible (SYS-xy-S) Protocols With Dual SDO-x
          3. 6.5.4.2.3 Source-Synchronous (SRC) Protocols
            1. 6.5.4.2.3.1 Output Clock Source Options
            2. 6.5.4.2.3.2 Output Bus Width Options
  8. 7 Register Maps
    1. 7.1 Device Configuration and Register Maps
      1. 7.1.1 DEVICE_ID_REG Register (address = 00h)
      2. 7.1.2 RST_PWRCTL_REG Register (address = 04h)
      3. 7.1.3 SDI_CTL_REG Register (address = 08h)
      4. 7.1.4 SDO_CTL_REG Register (address = 0Ch)
      5. 7.1.5 DATAOUT_CTL_REG Register (address = 10h)
      6. 7.1.6 RANGE_SEL_REG Register (address = 14h)
      7. 7.1.7 ALARM_REG Register (address = 20h)
      8. 7.1.8 ALARM_H_TH_REG Register (address = 24h)
      9. 7.1.9 ALARM_L_TH_REG Register (address = 28h)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Alarm Function
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Decoupling
      2. 8.3.2 Power Saving
        1. 8.3.2.1 NAP Mode
        2. 8.3.2.2 Power-Down (PD) Mode
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
6.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols With a Single SDO-x

As shown in Table 6-9, the host controller uses any of the four legacy, SPI-compatible protocols to read data from the device. These protocols are SPI-00-S, SPI-01-S, SPI-10-S, or SPI-11-S.

Table 6-9 SPI Protocols for Reading From the Device
PROTOCOLSCLK POLARITY
(At CS Falling Edge)		SCLK PHASE
(Capture Edge)		MSB BIT LAUNCH EDGESDI_CTL_REGSDO_CTL_REGDIAGRAM
SPI-00-SLowRisingCS falling00h00hFigure 6-28
SPI-01-SLowFalling1st SCLK rising01h00hFigure 6-28
SPI-10-SHighFallingCS falling02h00hFigure 6-29
SPI-11-SHighRising1st SCLK falling03h00hFigure 6-29

On power-up or after coming out of any asynchronous reset, the device supports the SPI-00-S protocol for data read and data write operations. To select a different SPI-compatible protocol for both the data transfer operations:

  1. Program the SDI_MODE[1:0] bits in the SDI_CTL_REG register. This first write operation adheres to the SPI-00-S protocol. Any subsequent data transfer frames adhere to the newly-selected protocol.
  2. Set the SDO_MODE[1:0] bits = 00b in the SDO_CTL_REG register.

Note:

The SPI transfer protocol selected by configuring the SDI_MODE[1:0] bits in the SDI_CTL_REG register determines the data transfer protocol for both write and read operations. Either data are read from the device or one of the SRC protocols is selected for data read, as explained in the Source-Synchronous (SRC) Protocols section. When data are read from the device, use the selected SPI protocol by configuring the SDO_MODE[1:0] bits = 00b in the SDO_CTL_REG register.

When using any of the SPI-compatible protocols, the RVS output remains low throughout the data transfer frame. See the Timing Requirements table for associated timing parameters.

Figure 6-28 and Figure 6-29 explain the details of the four protocols. The host controller uses a short data transfer frame to read only the required number of MSB bits from the 32-bit output data word. See the Data Transfer Frame section for details

If the host controller uses a long data transfer frame with SDO_CNTL_REG[7:0] = 00h, then the device exhibits daisy-chain operation. See the Multiple Devices: Daisy-Chain Topology section.

ADS8681W ADS8685W ADS8689W Standard SPI Timing Protocol(CPHA = 0, Single SDO-x)Figure 6-28 Standard SPI Timing Protocol
(CPHA = 0, Single SDO-x)
ADS8681W ADS8685W ADS8689W Standard SPI Timing Protocol(CPHA = 1, Single SDO-x)Figure 6-29 Standard SPI Timing Protocol
(CPHA = 1, Single SDO-x)