SBAS813 June 2018 ADS8688AT
PRODUCTION DATA.
The device supports a low-power standby mode (STDBY) in which only part of the circuit is powered down. The internal reference and buffer is not powered down, and therefore, the device can be quickly powered up in 20 µs on exiting the STDBY mode. When the device comes out of STDBY mode, the program registers are not reset to the default values.
To enter STDBY mode, execute a valid write operation as shown in Figure 92 to the command register with a STDBY command of 8200h. The command is executed and the device enters STDBY mode on the next CS rising edge following this write operation. The device remains in STDBY mode if no valid conversion command (AUTO_RST or MAN_Ch_n) is executed and SDI remains low (see the Continued Operation in the Selected Mode (NO_OP) section) during the subsequent data frames. When the device operates in STDBY mode, the program register settings can be updated (as explained in the Program Register Read/Write Operation section) using 16 SCLK cycles. However, if 32 complete SCLK cycles are provided, then the device returns invalid data on the SDO line because there is no ongoing conversion in STDBY mode. The program register read operation can take place normally during this mode.
In order to exit STDBY mode, as shown in Figure 93, a valid 16-bit write command must be executed to enter auto (AUTO_RST) or manual (MAN_CH_n) scan mode. The device starts exiting STDBY mode on the next CS rising edge. At the next CS falling edge, the device samples the analog input at the channel selected by the MAN_CH_n command or the first channel of the AUTO_RST mode sequence. To ensure that the input signal is sampled correctly, keep the minimum width of the CS signal at 20 µs after exiting STDBY mode so the device internal circuitry can be fully powered up and biased properly before taking the sample. The data output for the selected channel can be read during the same data frame, as explained in Figure 87.