SBAS707B June 2016 – January 2018 ADS8910B , ADS8912B , ADS8914B
PRODUCTION DATA.
This register configures the protocol for reading data from the device.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SSYNC_CLK_SEL[1:0] | 0 | DATA_RATE | SDO_WIDTH[1:0] | SDO_MODE[1:0] | |||
R/W-00b | R-0b | R/W-0b | R/W-00b | R/W-00b |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | SSYNC_CLK_SEL[1:0] | R/W | 00b | These bits select the source and frequency of the clock for the ADC-Clock-Master mode, and are valid only if SDO_MODE[1:0] = 11b. 00b = External SCLK echo 01b = Internal clock (INTCLK) 10b = Internal clock / 2 (INTCLK / 2) 11b = Internal clock / 4 (INTCLK / 4) |
5 | 0 | R | 0b | Reserved bit. Do not write. Reads return 0b. |
4 | DATA_RATE | R/W | 0b | This bit is ignored if SDO_MODE[1:0] = 00b. When SDO_MODE[1:0] = 11b: 0b = SDOs are updated at single data rate (SDR) with respect to the output clock 1b = SDOs are updated at double data rate (DDR) with respect to the output clock |
3-2 | SDO_WIDTH[1:0] | R/W | 00b | These bits set the width of the output bus. 0xb = Data are output only on SDO-0 10b = Data are output only on SDO-0 and SDO-1 11b = Data are output on SDO-0, SDO-1, SDO-2, and SDO-3 |
1-0 | SDO_MODE[1:0] | R/W | 00b | These bits select the protocol for reading data from the device. 00b = SDO follows the SPI protocol selected in the SDI_CNTL register 01b = SDO follows the SPI protocol selected in the SDI_CNTL register but with Early Data Launch feature enabled. See Table 6. 10b = Invalid configuration, not supported by the device 11b = SDO follows the source-synchronous protocol |