SLASF77A December 2022 – September 2023 AFE11612-SEP
PRODUCTION DATA
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | EALR_ CH0 | EALR_ CH1 | EALR_ CH2 | EALR_ CH3 | EALR_ LT_ LOW | EALR_ LT_ HIGH | EALR_ D1_ LOW | EALR_ D1_ HIGH | EALR_ D2_ LOW | EALR_ D2_ HIGH | EALR_ D1_ FAIL | EALR_ D1_ FAIL | ALARM_ LATCH_ DIS | Reserved | |
R-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R-0h |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
14 | EALR_CH0 | R/W | 0 | CH0 and (CH0+, CH1–) alarm enable bit. 0: The alarm is masked. When the input of CH0 or (CH0+, CH1–) is out of range, the ALARM pin does not go low, but the CH0_ALR bit is set. 1: The alarm is enabled, the CH0_ALR bit is set, and the ALARM pin goes low (if enabled) when the input of CH0 or (CH0+, CH1–) is out of range. |
13 | EALR_CH1 | R/W | 0 | CH1 alarm enable bit. 0: The alarm is masked. When the input of CH1 is out of range, the ALARM pin does not go low, but the CH1_ALR bit is set. 1: The alarm is enabled, the CH1_ALR bit is set, and the ALARM pin goes low (if enabled) when the input of CH1 is out of range. |
12 | EALR_CH2 | R/W | 0 | CH2 and (CH2+, CH3–) alarm enable bit. 0: The alarm is masked. When the input of CH2 or (CH2+, CH3–) is out of range, the ALARM pin does not go low, but the CH2_ALR bit is set. 1: The alarm is enabled, the CH2_ALR bit is set, and the ALARM pin goes low (if enabled) when the input of CH2 or (CH2+, CH3–) is out of range. |
11 | EALR_CH3 | R/W | 0 | CH3 alarm enable bit. 0: The alarm is masked. When the input of CH3 is out of range, the ALARM pin does not go low, but the CH3_ALR bit is set. 1: The alarm is enabled, the CH3_ALR bit is set, and the ALARM pin goes low (if enabled) when the input of CH3 is out of range. |
10 | EALR_LT_LOW | R/W | 0 | Local sensor low alarm enable bit. 0: The LT_Low alarm is masked. When LT is below the specified range, the ALARM pin does not go low, but the LT_Low_ALR bit is set. 1: The LT_Low alarm is enabled. When LT is below the specified range, the LT_Low_ALR bit is set (1) and the ALARM pin goes low (if enabled). |
9 | EALR_LT_HIGH | R/W | 0 | Local sensor high alarm enable bit. 0: The LT-High alarm is masked. When LT is above the specified range, the ALARM pin does not go low, but the LT_High_ALR bit is set. 1: The LT-High alarm is enabled. When LT is above the specified range, the LT-High-ALR bit is set (1) and the ALARM pin goes low (if enabled). |
8 | EALR_D1_LOW | R/W | 0 | D1 low alarm enable bit. 0: The D1-Low alarm is masked. When D1 is below the specified range, the ALARM pin does not go low, but the D1_Low_ALR bit is set. 1: The D1-Low alarm is enabled. When D1 is below the specified range, the D1_Low_ALR bit is set (1), and the ALARM pin goes low (if enabled). |
7 | EALR_D1_HIGH | R/W | 0 | D1 high alarm enable bit. 0: The D1-High alarm is masked. When D1 is above the specified range, the ALARM pin does not go low, but the D1_High_ALR bit is set. 1: The D1-High alarm is enabled. When D1 is above the specified range, the D1_High_ALR bit is set (1), and the ALARM pin goes low (if enabled). |
6 | EALR_D2_LOW | R/W | 0 | D2 low alarm enable bit. 0: The D2-Low alarm is masked. When D2 is below the specified range, the ALARM pin does not go low, but the D2_Low_ALR bit is set. 1: The D2-Low alarm is enabled. When D2 is below the specified range, the D2_Low_ALR bit is set (1), and the ALARM pin goes low (if enabled). |
5 | EALR_D2_HIGH | R/W | 0 | |
D2 high alarm enable bit. 0: The D2-High alarm is masked. When D2 is above the specified range, the ALARM pin does not go low, but the D2_High_ALR bit is set. 1: The D2-High alarm is enabled. When D2 is above the specified range, the D2_High_ALR bit is set (1), and the ALARM pin goes low (if enabled). | ||||
4 | EALR_D1_FAIL | R/W | 0 | D1 fail alarm enable bit. 0: The D1-FAIL alarm is masked. When D1 fails, the ALARM pin does not go low, but the D1_FAIL_ALR bit is set. 1: The D1-Fail alarm is enabled. When D1 fails, the D1_FAIL_ALR bit is set (1), the ALARM pin goes low (if enabled). |
3 | EALR_D2_FAIL | R/W | 0 | D2 fail alarm enable bit. 0: The D2-FAIL alarm is masked. When D2 fails, the ALARM pin does not go low, but the D2_FAIL_ALR bit is set. 1: The D2-Fail alarm is enabled. When D2 fails, the D2_FAIL_ALR bit is set (1), the ALARM pin goes low (if enabled). |
2 | ALARM_LATCH_ DIS |
R/W | 0 | Alarm latch disable bit. 0: The status register bits are latched. When an alarm occurs, the corresponding alarm bit is set (1). The alarm bit remains 1 until the error condition subsides and the status register is read. Before reading, the alarm bit is not cleared (0) even if the alarm condition disappears. 1: The status register bits are not latched. When the alarm condition subsides, the alarm bits are cleared regardless of whether the status register is read or not. |