SLASF77A December 2022 – September 2023 AFE11612-SEP
PRODUCTION DATA
The SPI shift register is 24 bits wide. Data are loaded into the device MSB first as a 24-bit word under the control of the serial clock input, SCLK. The CS falling edge starts the communication cycle. Data are latched into the SPI shift register on the SCLK falling edge, while CS is low. When CS is high, the SCLK and SDI signals are blocked out and the SDO line is in a high-impedance state. The contents of the SPI shift register are loaded into the device internal register on the CS rising edge (with delay). During the transfer, the command is decoded and new data are transferred into the proper registers.
The serial interface functions with both a continuous and non-continuous serial clock. A continuous SCLK source can only be used if CS is held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used and CS must be taken high after the final clock to latch the data.