SLASF77A December 2022 – September 2023 AFE11612-SEP
PRODUCTION DATA
The device has several 16-bit registers that consist of a high byte (8 MSBs) and a low byte (8 LSBs). An 8-bit register pointer points to the proper register. The pointer does not change after an operation. Table 7-10 lists the registers for the device. The default values are for SPI operation; see the following subsections for I2C default values.
ADDR (HEX) | REGISTER | TYPE | RESET (HEX) | BIT DESCRIPTION | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
00 | LT_ TEMP |
R | 0000 | LT_DATA [11:0] | Reserved | ||||||||||||||
01 | D1_ TEMP |
R | 0000 | D1_DATA [11:0] | Reserved | ||||||||||||||
02 | D2_ TEMP |
R | 0000 | D2_DATA [11:0] | Reserved | ||||||||||||||
0A | TEMP_ CONFIG |
R/W | 003C | Reserved | D2EN | D1EN | LTEN | RC | Reserved | ||||||||||
0B | TEMP_ CONV_ RATE |
R/W | 0007 | Reserved | RATE[2:0] | ||||||||||||||
21 | D1_N_ ADJUST |
R/W | 0000 | Reserved | N_ADJUST[7:0] | ||||||||||||||
22 | D2_N_ ADJUST |
R/W | 0000 | Reserved | N_ADJUST[7:0] | ||||||||||||||
23 | ADC_0 | R | 0000 | Reserved | ADC[11:0] | ||||||||||||||
24 | ADC_1 | R | 0000 | Reserved | ADC[11:0] | ||||||||||||||
25 | ADC_2 | R | 0000 | Reserved | ADC[11:0] | ||||||||||||||
26 | ADC_3 | R | 0000 | Reserved | ADC[11:0] | ||||||||||||||
27 | ADC_4 | R | 0000 | Reserved | ADC[11:0] | ||||||||||||||
28 | ADC_5 | R | 0000 | Reserved | ADC[11:0] | ||||||||||||||
29 | ADC_6 | R | 0000 | Reserved | ADC[11:0] | ||||||||||||||
2A | ADC_7 | R | 0000 | Reserved | ADC[11:0] | ||||||||||||||
2B | ADC_8 | R | 0000 | Reserved | ADC[11:0] | ||||||||||||||
2C | ADC_9 | R | 0000 | Reserved | ADC[11:0] | ||||||||||||||
2D | ADC_10 | R | 0000 | Reserved | ADC[11:0] | ||||||||||||||
2E | ADC_11 | R | 0000 | Reserved | ADC[11:0] | ||||||||||||||
2F | ADC_12 | R | 0000 | Reserved | ADC[11:0] | ||||||||||||||
30 | ADC_13 | R | 0000 | Reserved | ADC[11:0] | ||||||||||||||
31 | ADC_14 | R | 0000 | Reserved | ADC[11:0] | ||||||||||||||
32 | ADC_15 | R | 0000 | Reserved | ADC[11:0] | ||||||||||||||
33 | DAC_0 | R/W | 0000 | Reserved | DAC[11:0] | ||||||||||||||
34 | DAC_1 | R/W | 0000 | Reserved | DAC[11:0] | ||||||||||||||
35 | DAC_2 | R/W | 0000 | Reserved | DAC[11:0] | ||||||||||||||
36 | DAC_3 | R/W | 0000 | Reserved | DAC[11:0] | ||||||||||||||
37 | DAC_4 | R/W | 0000 | Reserved | DAC[11:0] | ||||||||||||||
38 | DAC_5 | R/W | 0000 | Reserved | DAC[11:0] | ||||||||||||||
39 | DAC_6 | R/W | 0000 | Reserved | DAC[11:0] | ||||||||||||||
3A | DAC_7 | R/W | 0000 | Reserved | DAC[11:0] | ||||||||||||||
3B | DAC_8 | R/W | 0000 | Reserved | DAC[11:0] | ||||||||||||||
3C | DAC_9 | R/W | 0000 | Reserved | DAC[11:0] | ||||||||||||||
3D | DAC_10 | R/W | 0000 | Reserved | DAC[11:0] | ||||||||||||||
3E | DAC_11 | R/W | 0000 | Reserved | DAC[11:0] | ||||||||||||||
3F | DAC_0_ CLR |
R/W | 0000 | Reserved | DAC_CLR[11:0] | ||||||||||||||
40 | DAC_1_ CLR |
R/W | 0000 | Reserved | DAC_CLR[11:0] | ||||||||||||||
41 | DAC_2_ CLR |
R/W | 0000 | Reserved | DAC_CLR[11:0] | ||||||||||||||
42 | DAC_3_ CLR |
R/W | 0000 | Reserved | DAC_CLR[11:0] | ||||||||||||||
43 | DAC_4_ CLR |
R/W | 0000 | Reserved | DAC_CLR[11:0] | ||||||||||||||
44 | DAC_5_ CLR |
R/W | 0000 | Reserved | DAC_CLR[11:0] | ||||||||||||||
45 | DAC_6_ CLR |
R/W | 0000 | Reserved | DAC_CLR[11:0] | ||||||||||||||
46 | DAC_7_ CLR |
R/W | 0000 | Reserved | DAC_CLR[11:0] | ||||||||||||||
47 | DAC_8_ CLR |
R/W | 0000 | Reserved | DAC_CLR[11:0] | ||||||||||||||
48 | DAC_9_ CLR |
R/W | 0000 | Reserved | DAC_CLR[11:0] | ||||||||||||||
49 | DAC_10_ CLR |
R/W | 0000 | Reserved | DAC_CLR[11:0] | ||||||||||||||
4A | DAC_11_ CLR |
R/W | 0000 | Reserved | DAC_CLR[11:0] | ||||||||||||||
4B | GPIO | R/W | 00FF | Reserved | GPIO[7:0] | ||||||||||||||
4C | AFE_ CONFIG_0 |
R/W | 2000 | Reserved | CMODE | ICONV | ILDAC | ADC_ REF_ INT |
EN_ ALARM |
Reserved | DAVF | GALR | Reserved | ||||||
4D | AFE_ CONFIG_1 |
R/W | 0070 | Reserved | CONV_ RATE_1 |
CONV_ RATE_0 |
CH_ FALR_ CT_2 |
CH_ FALR_ CT_1 |
CH_ FALR_ CT_0 |
TEMP_ FALR_ CT_1 |
TEMP_ FALR_ CT_0 |
Reserved | |||||||
4E | ALR_CTRL | R/W | 0000 | Reserved | EALR_ CH0 |
EALR_ CH1 |
EALR_ CH2 |
EALR_ CH3 |
EALR_ LT_ LOW |
EALR_ LT_ HIGH |
EALR_ D1_ LOW |
EALR_ D1_ HIGH |
EALR_ D2_ LOW |
EALR_ D2_ HIGH |
EALR_ D1_ FAIL |
EALR_ D2_ FAIL |
ALARM_ LATCH_ DIS |
Reserved | |
4F | STATUS | R | 0000 | Reserved | CH0_ ALR |
CH1_ ALR |
CH2_ ALR |
CH3_ ALR |
LT_ LOW_ ALR |
LT_ HIGH_ ALR |
D1_ LOW_ ALR |
D1_ HIGH_ ALR |
D2_ LOW_ ALR |
D2_ HIGH_ ALR |
D1_ FAIL_ ALR |
D2_ FAIL_ ALR |
THERM_ ALR |
Reserved | |
50 | ADC_CH0 | R/W | 0000 | Reserved | SE0 | SE1 | DF (CH0+, CH1-) |
SE2 | SE3 | DF (CH2+, CH3-) |
SE4 | SE5 | SE6 | SE7 | SE8 | SE9 | SE10 | SE11 | SE12 |
51 | ADC_CH1 | R/W | 0000 | Reserved | SE13 | SE14 | SE15 | Reserved | |||||||||||
52 | ADC_GAIN | R/W | FFFF | ADG0 | ADG1 | ADG2 | ADG3 | ADG4 | ADG5 | ADG6 | ADG7 | ADG8 | ADG9 | ADG10 | ADG11 | ADG12 | ADG13 | ADG14 | ADG15 |
53 | AUTO_DAC_ CLR_ SOURCE |
R/W | 0004 | Reserved | CH0_ ALR_ CLR |
CH1_ ALR |
CH2_ ALR_ CLR |
CH3_ ALR_ CLR |
LT_ LOW_ ALR_ CLR |
LT_ HIGH_ ALR_ CLR |
D1_ LOW_ ALR_ CLR |
D1_ HIGH_ ALR_ CLR |
D2_ LOW_ ALR_ CLR |
D2_ HIGH_ ALR_ CLR |
D1_ FAIL_ ALR_ CLR |
D2_ FAIL_ ALR_ CLR |
THERM_ ALR_ CLR |
Reserved | |
54 | AUTO_DAC_ CLR_EN |
R/W | 0000 | Reserved | ACLR[11:0] | Reserved | |||||||||||||
55 | SW_DAC_ CLR |
R/W | 0000 | Reserved | ICLR[11:0] | Reserved | |||||||||||||
56 | HW_DAC_ CLR_EN_0 |
R/W | 0000 | Reserved | H0CLR[11:0] | Reserved | |||||||||||||
57 | HW_DAC_ CLR_EN_1 |
R/W | 0000 | Reserved | H1CLR[11:0] | Reserved | |||||||||||||
58 | DAC_CONFIG | R/W | 0000 | Reserved | SLDA[11:0] | ||||||||||||||
59 | DAC_GAIN | R/W | 0000 | Reserved | DAC_GAIN[11:0] | ||||||||||||||
5A | IN_0_ HIGH_ THRESHOLD |
R/W | 0FFF | Reserved | THRH[11:0] | ||||||||||||||
5B | IN_0_ LOW_ THRESHOLD |
R/W | 0000 | Reserved | THRL[11:0] | ||||||||||||||
5C | IN_1_ HIGH_ THRESHOLD |
R/W | 0FFF | Reserved | THRH[11:0] | ||||||||||||||
5D | IN_1_ LOW_ THRESHOLD |
R/W | 0000 | Reserved | THRL[11:0] | ||||||||||||||
5E | IN_2_ HIGH_ THRESHOLD |
R/W | 0FFF | Reserved | THRH[11:0] | ||||||||||||||
5F | IN_2_ LOW_ THRESHOLD |
R/W | 0000 | Reserved | THRL[11:0] | ||||||||||||||
60 | IN_3_ HIGH_ THRESHOLD |
R/W | 0FFF | Reserved | THRH[11:0] | ||||||||||||||
61 | IN_3_ LOW_ THRESHOLD |
R/W | 0000 | Reserved | THRL[11:0] | ||||||||||||||
62 | LT_ HIGH_ THRESHOLD |
R/W | 07FF | Reserved | THRH[11:0] | ||||||||||||||
63 | LT_ LOW_ THRESHOLD |
R/W | 0800 | Reserved | THRL[11:0] | ||||||||||||||
64 | D1_ HIGH_ THRESHOLD |
R/W | 07FF | Reserved | THRH[11:0] | ||||||||||||||
65 | D1_ LOW_ THRESHOLD |
R/W | 0800 | Reserved | THRL[11:0] | ||||||||||||||
66 | D2_ HIGH_ THRESHOLD |
R/W | 07FF | Reserved | THRH[11:0] | ||||||||||||||
67 | D2_ LOW_ THRESHOLD |
R/W | 0800 | Reserved | THRL[11:0] | ||||||||||||||
68 | HYST_0 | R/W | 0810 | Reserved | CH0_HYS [6:0] | CH1_HYS [6:0] | Reserved | ||||||||||||
69 | HYST_1 | R/W | 0810 | Reserved | CH2_HYS [6:0] | CH3_HYS [6:0] | Reserved | ||||||||||||
6A | HYST_2 | R/W | 2108 | Reserved | D2_ HYS_7 |
D2_ HYS_6 |
D2_ HYS_5 |
D2_ HYS_4 |
D2_ HYS_3 |
D1_ HYS_7 |
D1_ HYS_6 |
D1_ HYS_5 |
D1_ HYS_4 |
D1_ HYS_3 |
LT_ HYS_7 |
LT_ HYS_6 |
LT_ HYS_5 |
LT_ HYS_4 |
LT_ HYS_3 |
6B | PWR_DOWN | R/W | 0000 | Reserved | PADC | PREF | PDAC0 | PDAC1 | PDAC2 | PDAC3 | PDAC4 | PDAC5 | PDAC6 | PDAC7 | PDAC8 | PDAC9 | PDAC10 | PDAC11 | Reserved |
6C | DEVICE_ID | R | 1220 | DEVICE_ID[15:0] | |||||||||||||||
7C | SW_RST | R/W | N/A | SW_RST[15:0] |