SLASF77A December 2022 – September 2023 AFE11612-SEP
PRODUCTION DATA
This register determines which DAC is in a clear state when the DAC-CLR-1 pin goes low.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | H1CLR | Reserved | |||||||||||||
R/W-0 | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
14-3 | H1CLR | R/W | 0h | Hardware clear DAC-n enable 1 bit. If H1CLRn = 0, pulling the DAC-CLR-1 pin low does not effect the state of DAC-n If H1CLRn = 1, DAC-n is forced into a clear state when the DAC-CLR-1 pin goes low |