SLASF77A December 2022 – September 2023 AFE11612-SEP
PRODUCTION DATA
See Figure 7-9 for the structure of the DAC register and DAC latch. The contents of the DAC-n latch determine the output level of the DAC-n pin. After writing to the DAC-n-data register, the DAC latch updates when the synchronous DAC loading signal triggers. Set the ILDAC bit in AFE configuration register 0 to trigger the loading signal.