SLASF77A December 2022 – September 2023 AFE11612-SEP
PRODUCTION DATA
In standalone mode, as shown in Figure 7-26, each device has an SPI bus. The serial clock can be continuous or gated. The first CS falling edge starts the operation cycle. Exactly 24 falling clock edges must be applied before CS is brought high again. If CS is brought high before the 24th falling SCLK edge, or if more than 24 SCLK falling edges are applied before CS is brought high, then the input data are incorrect. The device input register is updated from the shift register on the CS rising edge, and data are automatically transferred to the addressed registers as well. For another serial transfer to occur, CS must be brought low again. Figure 7-27 and Figure 7-28 show write and read operations in standalone mode.