SLASF77A December 2022 – September 2023 AFE11612-SEP
PRODUCTION DATA
The SLDA-n (synchronous load) bit of the DAC configuration register must be set to 1 to enable proper DAC output update operation.
SLDA-n BIT | WRITING TO ILDAC BIT | OPERATION |
---|---|---|
0 | Don't care | Reserved for DACs not being updated. |
1 | 1 | Simultaneously update all DACs by internal trigger. Writing 1 to the ILDAC bit generates an internal load DAC trigger signal that updates the DAC-n latches and DAC-n outputs with the contents of the corresponding DAC-n-data register. |
The value of the DAC-n-data register is transferred to the DAC-n latch only after an active DAC synchronous loading signal (ILDAC) occurs, which immediately updates the DAC-n output. Under synchronous loading operation, writing data into a DAC-n-data register changes only the value in that register, but not the content of DAC-n latch nor the output of DAC-n, until the synchronous load signal occurs.
The DAC synchronous load is triggered by writing 1 to the ILDAC bit in AFE configuration register 0. When this DAC synchronous load signal occurs, all DACs with the SLDA-n bit set to 1 are simultaneously updated with the value of the corresponding DAC-n-data register. By setting the SLDA-n bit properly, several DACs can be updated at the same time. For example, to update DAC0 and DAC1 synchronously, set bits SLDA-0 and SLDA-1 to 1 first, and then write the proper values into the DAC-0-data and DAC-1-data registers, respectively. After this presetting, set the ILDAC bit to 1 to simultaneously load DAC0 and DAC1. The outputs of DAC0 and DAC1 change at the same time.
The device updates the DAC latch only if the latch was accessed from the last time ILDAC was issued, thereby eliminating any unnecessary glitches. Any DAC channels that are not accessed are not reloaded again. When the DAC latch is updated, the corresponding output changes to the new level immediately.
When DACs are cleared by an external DAC-CLR-n or by the internal CLR bit, the DAC latch is loaded with the predefined value of the DAC-n-CLR-setting register and the output is set to the corresponding level immediately, regardless of the SLDA-n bit value. However, the DAC data register does not change.