SLASF77A December 2022 – September 2023 AFE11612-SEP
PRODUCTION DATA
The maximum conversion rate is 500 kSPS for a single channel in auto mode, as shown in Table 7-7. The conversion rate is programmable through the CONV-RATE-[1:0] bits of the AFE configuration register 1. When more than one channel is selected, the conversion rate is divided by the number of channels selected in ADC channel register 0 and ADC channel register 1. In auto mode, the CONV-RATE-[1:0] bits determine the actual conversion rate. In direct mode, the CONV-RATE-[1:0] bits limit the maximum possible conversion rate. The actual conversion rate in direct mode is determined by the rate of the conversion trigger. Be aware that when a trigger is issued, there can be a delay of up to 4 µs to internally synchronize and initiate the start of the sequential channel conversion process. In both direct and auto modes, when the CONV-RATE-[1:0] bits are set to a value other than the maximum rate (00), nap mode is activated between conversions. By activating nap mode, the AIDD supply current is reduced; see Figure 6-42.
CONV-RATE-1 | CONV-RATE-0 | tACQ (µs) |
tCONV (µs) |
NAP ENABLED |
THROUGHPUT (Single-Channel Auto Mode) |
---|---|---|---|---|---|
0 | 0 | 0.375 | 1.625 | No | 500 kSPS (default) |
0 | 1 | 2.375 | 1.625 | Yes | 250 kSPS |
1 | 0 | 6.375 | 1.625 | Yes | 125 kSPS |
1 | 1 | 14.375 | 1.625 | Yes | 62.5 kSPS |