SLASF77A December 2022 – September 2023 AFE11612-SEP
PRODUCTION DATA
The preferred (not required) order for applying power is IOVDD, DVDD or AVDD, and then AVCC. All registers initialize to default values after these supplies are established. Communication with the device is valid after a 250-µs maximum power-on reset delay. The default state of all analog blocks is off as determined by the power-down register (6Bh). Before writing to this register, issue a hardware reset to maintain specified device operation. Device communication is valid after a maximum 250-µs reset delay from the RESET rising edge. If DVDD falls to less than 2.7 V, the minimum supply value of DVDD, either issue a hardware or power-on reset to resume proper operation.
To avoid activating the device ESD protection diodes, do not apply the GPIO-4, GPIO-5, GPIO-6, and GPIO-7 inputs before AVDD is established. Also, if using the external reference configuration of the ADC, do not apply ADC-REF-IN/CMP before AVDD.