SLASF77A December 2022 – September 2023 AFE11612-SEP
PRODUCTION DATA
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | ADC [11:0] | ||||||||||||||
R-0h | R-0h |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
11-0 | ADC | R | 000h | ADC data, stored in binary format. |
Four ADC data registers are available. The ADC-n-data registers (where n = 0 to 15) store the conversion results of the corresponding analog channel-n, as shown in Table 7-19.
INPUT CHANNEL | INPUT TYPE | CONVERSION RESULT STORED IN | FORMAT |
---|---|---|---|
Channel 0 | Single-ended | ADC-0-data register | Straight binary |
Channel 1 | Single-ended | ADC-1-data register | Straight binary |
Channel 2 | Single-ended | ADC-2-data register | Straight binary |
Channel 3 | Single-ended | ADC-3-data register | Straight binary |
CH0+ or CH1– | Differential | ADC-0-data register | 2's complement |
CH2+ or CH3– | Differential | ADC-2-data register | 2's complement |
Channel 4 | Single-ended | ADC-4-data register | Straight binary |
Channel 5 | Single-ended | ADC-5-data register | Straight binary |
Channel 6 | Single-ended | ADC-6-data register | Straight binary |
Channel 7 | Single-ended | ADC-7-data register | Straight binary |
Channel 8 | Single-ended | ADC-8-data register | Straight binary |
Channel 9 | Single-ended | ADC-9-data register | Straight binary |
Channel 10 | Single-ended | ADC-10-data register | Straight binary |
Channel 11 | Single-ended | ADC-11-data register | Straight binary |
Channel 12 | Single-ended | ADC-12-data register | Straight binary |
Channel 13 | Single-ended | ADC-13-data register | Straight binary |
Channel 14 | Single-ended | ADC-14-data register | Straight binary |
Channel 15 | Single-ended | ADC-15-data register | Straight binary |