SLASF77A December 2022 – September 2023 AFE11612-SEP
PRODUCTION DATA
The host can access all 16, double-buffered ADC data registers, as shown in Figure 7-3. The conversion result from the analog input with channel address n (where n = 0 to 15) is stored in the ADC-n-data register. When the conversion of an individual channel completes, the data are immediately transferred into the corresponding ADC-n temporary (TMPRY) register, the first stage of the data buffer. When the conversion of the last channel completes, all data in the ADC-n TMPRY registers are simultaneously transferred into the corresponding ADC-n-data registers, the second stage of the data buffer. However, if a data transfer is in progress between any ADC-n-data register and the AFE shift register, no ADC-n-data registers are updated until the data transfer is complete. The conversion result from channel address n is stored in the ADC-n-data register. For example, the result from channel 0 is stored in the ADC-0-data register, and the result from channel 3 is stored in the ADC-3-data register.