SLASF77A December 2022 – September 2023 AFE11612-SEP
PRODUCTION DATA
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | CMODE | ICONV | ILDAC | ADC-REF-INT | EN-ALARM | Reserved | DAVF | GALR | Reserved | ||||||
R-0h | R/W-1 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R-0 | R-0 | R-0 | R-0h |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
13 | CMODE | R/W | 1 | ADC conversion mode bit. This bit selects
between the two operating conversion modes (direct or auto). 0:
Direct mode. The analog inputs specified in the ADC channel
registers are converted sequentially (see the ADC channel registers) one time. When one set of
conversions are complete, the ADC is idle and waits for a new
trigger. 1: Auto mode. The analog inputs specified in the AFE channel registers are converted sequentially and repeatedly (see the ADC channel registers). When one set of conversions are complete, the ADC multiplexer returns to the first channel and repeats the process. Repetitive conversions continue until the CMODE bit is cleared (0). |
12 | ICONV | R/W | 0 | Internal conversion bit. Set this bit to 1 to start the ADC conversion internally. The bit is automatically cleared (0) after the ADC conversion starts. |
11 | ILDAC | R/W | 0 | Load DAC bit. Set this bit to 1 to synchronously load the DAC data registers, which are programmed for synchronous update mode (SLDAC-n = 1). The device updates the DAC latch only if the ILDAC bit is set (1), thereby eliminating any unnecessary glitches. Any DAC channels that are not accessed are not reloaded. When the DAC latch is updated, the corresponding output changes to the new level immediately. This bit is cleared (0) after the DAC data register is updated. |
10 | ADC-REF-INT | R/W | 0 | ADC VREF select bit. 0: The
internal reference buffer is off and the external reference drives
the ADC. 1: The internal buffer is on and the internal reference drives the ADC. Note that a compensation capacitor is required. |
9 | EN-ALARM | R/W | 0 | Enable ALARM pin
bit. 0: The ALARM pin is disabled 1: The ALARM pin is enabled |
7 | DAVF | R | ADC Data available flag bit. For direct
mode only. Always cleared (set to 0) in Auto mode. 0: The ADC conversion is in progress (data are not ready) or the ADC is in auto mode. 1: The ADC conversions are complete and new data are available. In direct mode, the DAVF bit sets the DAV pin. DAV goes low when DAVF is 1, and goes high when DAVF is 0. In auto mode, DAVF is always cleared to 0. However, a 1-µs pulse (active low) appears on the DAV pin when the last input specified in the ADC channel registers is converted. DAVF is cleared to 0 in one of three ways: by reading the ADC data register, by starting a new ADC conversion, or by writing 0 to this bit. Reading the status register does not clear this bit. | |
6 | GALR | R | 0 | Global alarm bit. This bit is the OR function of all individual alarm bits of the status register. This bit is set (1) when any alarm condition occurs, and remains 1 until the status register is read. This bit is cleared (0) after reading the status register. |