SBASAC2 june   2023 AFE43902-Q1 , AFE53902-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Voltage Output
    6. 6.6  Electrical Characteristics: ADC Input
    7. 6.7  Electrical Characteristics: General
    8. 6.8  Timing Requirements: I2C Standard Mode
    9. 6.9  Timing Requirements: I2C Fast Mode
    10. 6.10 Timing Requirements: I2C Fast Mode Plus
    11. 6.11 Timing Requirements: SPI Write Operation
    12. 6.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    14. 6.14 Timing Requirements: PWM Output
    15. 6.15 Timing Diagrams
    16. 6.16 Typical Characteristics: Voltage Output
    17. 6.17 Typical Characteristics: ADC
    18. 6.18 Typical Characteristics: General
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Analog Front End (AFE) Architecture
      2. 7.3.2 Programming Interface
      3. 7.3.3 Nonvolatile Memory (NVM)
        1. 7.3.3.1 NVM Cyclic Redundancy Check (CRC)
          1. 7.3.3.1.1 NVM-CRC-FAIL-USER Bit
          2. 7.3.3.1.2 NVM-CRC-FAIL-INT Bit
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 External Reset
      6. 7.3.6 Register-Map Lock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital-to-Analog Converter (DAC) Mode
        1. 7.4.1.1 Voltage Reference and DAC Transfer Function
          1. 7.4.1.1.1 Power-Supply as Reference
          2. 7.4.1.1.2 Internal Reference
          3. 7.4.1.1.3 External Reference
      2. 7.4.2 Pulse-Width Modulation (PWM) Mode
      3. 7.4.3 Analog-to-Digital Converter (ADC) Mode
      4. 7.4.4 Multislope Thermal Foldback Mode
        1. 7.4.4.1 Thermistor Linearization
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-x-VOUT-CMP-CONFIG Register (address = 15h, 03h) [reset = 0400h]
      3. 7.6.3  COMMON-CONFIG Register (address = 1Fh) [reset = 03F9h]
      4. 7.6.4  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      5. 7.6.5  COMMON-PWM-TRIG Register (address = 21h) [reset = 0001h]
      6. 7.6.6  GENERAL-STATUS Register (address = 22h) [reset = 2068h]
      7. 7.6.7  DEVICE-MODE-CONFIG Register (address = 25h) [reset = 8040h]
      8. 7.6.8  INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      9. 7.6.9  STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      10. 7.6.10 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      11. 7.6.11 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      12. 7.6.12 Xx-TEMPERATURE Register (SRAM address = 20h, 22h, 24h) [reset = 0000h]
      13. 7.6.13 Yx-TEMPERATURE Register (SRAM address = 21h, 23h, 25h) [reset = 0000h]
      14. 7.6.14 Xx-OUTPUT Register (SRAM address = 26h, 28h, 2Ah, 2Ch) [reset = 0000h]
      15. 7.6.15 Yx-OUTPUT Register (SRAM address = 27h, 29h, 2Bh, 2Dh) [reset = 0000h]
      16. 7.6.16 PWM-FREQUENCY Register (SRAM address = 2Eh) [reset = 0000h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Multislope Thermal Foldback Using the AFE53902-Q1 and Voltage Output
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 Multislope Thermal Foldback Using the AFE43902-Q1 and PWM Output
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Performance Plots
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.2 Detailed Design Procedure

The state machine converts a temperature input to a PWM output based on the values saved in the thermal foldback profile. The voltage output from the temperature sensor is read by the ADC and converted to an ADC code. There are three X and Y points available to map the ADC codes (X points) to a temperature (Y points). These points can be used to apply linearization to the temperature sensor output. The ADC is 10-bits, so the maximum code is 1023d. Equation 9 calculates the ADC output code based on the voltage input.

Equation 9. ADC_CODE=VIN×210VREF

This application example uses the 5-V VDD as the ADC reference. Equation 10 calculates the ADC code for a 2.5-V input.

Equation 10. ADC_CODE=2.5 V×2105 V=512d

Table 8-6 shows the ADC code to temperature mapping used in this application example. An NTC resistor is used as the temperature sensor. Higher ADC codes correspond to a lower temperature.

Table 8-6 Thermal Foldback Profile: ADC to Temperature
ADC CODE TEMPERATURE
0x000 100°C
0x200 50°C
0x3FF 0°C

The PWM frequency is set in the PWM-FREQUENCY SRAM location (SRAM: 0x2E). Table 7-1 defines the codes for each available frequency. There are four X and Y points available to map the temperature (X points) to an output duty cycle (Y points). The PWM duty-cycle output is configured by a 7-bit code. The maximum code is 127d. Equation 11 calculates the duty-cycle:

Equation 11. D U T Y _ C Y C L E _ C O D E = D u t y _ C y c l e ( % ) × 2 7 1 0 0 %

For a 50% duty cycle, Equation 11 calculates the duty-cycle code as 64d.

Note: A duty-cycle code of 127d sets the PWM duty cycle to 100% which does not follow Equation 11. Table 7-2 provides the details of this exception.

Table 8-7 shows the temperature to output duty cycle mapping used in this application example. The profile can have both negative and positive slopes.

Table 8-7 Thermal Foldback Profile: Temperature to PWM
TEMPERATURE OUTPUT DUTY CYCLE (CODE)
20°C 78% (0x64)
50°C 100% (0x7F)
75°C 63% (0x51)
100°C 0% (0x00)

Follow these guidelines to setup the registers on the AFE43902-Q1:

  • Set the VREF/MODE pin low to enable the digital pins for programming mode.
  • Stop the state machine before updating the application parameters by writing 0 to the STATE-MACHINE-CONFIG0 register.
  • If the PWM generator is already running, the PWM generator needs to be stopped before any changes to the PWM frequency take effect. Write a 0 to the START-FUNCTION bit in the COMMON-PWM-TRIG register (0x21) to stop the PWM generator. The PWM generator is automatically started when the state machine is enabled.
  • Set all of the application parameters shown in Table 8-8. These locations must be used to save the settings in the NVM. For example, the DAC register location for the PWM-FREQUENCY are not mapped to the NVM and is not saved when an NVM write is triggered.
  • Configure the reference for both channels in the DAC-x-VOUT-CMP-CONFIG registers.
    • Configure channel 0 as an ADC input by setting the CMP-x-EN bit to 1.
  • Power on the ADC channel using the COMMON-CONFIG register.
  • Set the DEVICE-MODE-CONFIG register to 0x9000.
  • Start the state machine by writing 0x3 to the STATE-MACHINE-CONFIG0.
  • Trigger an NVM write by setting the NVM-PROG bit in the COMMON-TRIGGER register (0x20) to 1.
  • Set the VREF/MODE pin high to enable the digital pins for standalone mode. This setting is required to see the PWM output on the digital pin.
Table 8-8 Application Parameters
REGISTER FIELD NAME ADDRESS[FIELD] ADDRESS LOCATION
X1-TEMPERATURE 0x20[10:1] SRAM
Y1-TEMPERATURE 0x21[7:0] SRAM
X2-TEMPERATURE 0x22[10:1] SRAM
Y2-TEMPERATURE 0x23[7:0] SRAM
X3-TEMPERATURE 0x24[10:1] SRAM
Y3-TEMPERATURE 0x25[7:0] SRAM
X1-OUTPUT 0x26[7:0] SRAM
Y1-OUTPUT 0x27[6:0] SRAM
X2-OUTPUT 0x28[7:0] SRAM
Y2-OUTPUT 0x29[6:0] SRAM
X3-OUTPUT 0x2A[7:0] SRAM
Y3-OUTPUT 0x2B[6:0] SRAM
X4-OUTPUT 0x2C[7:0] SRAM
Y4-OUTPUT 0x2D[6:0] SRAM
PWM-FREQUENCY 0x2E[11:7] SRAM
DAC-0-VOUT-CMP-CONFIG 0x15[12:10][4:0] Register
DAC-1-VOUT-CMP-CONFIG 0x03[12:10][4:0] Register
COMMON-CONFIG 0x1F[15:0] Register
DEVICE-MODE-CONFIG 0x25[15:0] Register
STATE-MACHINE-CONFIG0 0x27[2:0] Register

Only the bits listed in the address column of Table 8-8 are saved in NVM and used in the state machine. For example, only bits 12 to 10 and 4 to 0 are saved in NVM for the DAC-x-VOUT-CMP-CONFIG registers.

The pseudocode for this application example is as follows: 

//SYNTAX: WRITE <REGISTER NAME(Hex Code)>, <MSB DATA>, <LSB DATA>
//Stop the state machine
WRITE STATE-MACHINE-CONFIG0(0x27), 0x00, 0x03
//Stop the PWM generator
WRITE COMMON-PWM-TRIG(0x21), 0x00, 0x00
//Set the PWM frequncy (this is the device default)
WRITE PWM-FREQUENCY(SRAM 0x2E), 0x05, 0x80
//Set the thermal foldback profile values
//The PWM duty cycle is a 7-bit value
WRITE X1-TEMPERATURE(SRAM 0x20), 0x00, 0x00
WRITE Y1-TEMPERATURE(SRAM 0x21), 0x00, 0x64
WRITE X2-TEMPERATURE(SRAM 0x22), 0x04, 0x00
WRITE Y2-TEMPERATURE(SRAM 0x23), 0x00, 0x32
WRITE X3-TEMPERATURE(SRAM 0x24), 0x07, 0xFF
WRITE Y3-TEMPERATURE(SRAM 0x25), 0x00, 0x00
WRITE X1-OUTPUT(SRAM 0x26), 0x00, 0x14
WRITE Y1-OUTPUT(SRAM 0x27), 0x03, 0x64
WRITE X2-OUTPUT(SRAM 0x28), 0x00, 0x32
WRITE Y2-OUTPUT(SRAM 0x29), 0x03, 0x7F
WRITE X3-OUTPUT(SRAM 0x2A), 0x00, 0x4B
WRITE Y3-OUTPUT(SRAM 0x2B), 0x02, 0x51
WRITE X4-OUTPUT(SRAM 0x2C), 0x00, 0x64
WRITE Y4-OUTPUT(SRAM 0x2D), 0x00, 0x00
//Set the channel 0 reference to VDD, enable the comparator for ADC mode (this is the device default) 
WRITE DAC-0-VOUT-CMP-CONFIG(0x15), 0x04, 0x01
//Power on the ADC channel 
WRITE COMMON-CONFIG(0x1F), 0x03, 0xFF
//Set the device mode (this is the device default) 
WRITE DEVICE-MODE-CONFIG(0x25), 0x90, 0x00
//Start the state machine
WRITE STATE-MACHINE-CONFIG(0x27), 0x00, 0x03
//Save settings to NVM
WRITE COMMON-TRIGGER(0x20), 0x00, 0x02