9.2.1 Design Requirements

The AFE architecture is very flexible, and can be used for both high-performance saturation of peripheral capillary oxygen (SpO2) applications as well as low-power, battery-operated heart-rate monitoring (HRM) applications as a result of this flexibility. The high dynamic range of the AFE enables excellent SNR for the signal of interest (usually small in amplitude) even in the presence of large-signal artifacts resulting from ambient and motion changes.

9.2.2 Detailed Design Procedure

The following important factors are key to extracting the full performance benefit from the AFE:

1. Good optics including bright LEDs and high-sensitivity photodiodes
2. Good mechanical design
3. A calibration loop that sets the optimal AFE settings based on the signal conditions

TI recommends that a system-level budgeting of dynamic range be initially done based on the following factors:

1. The range of the dc signal currents that are input to the AFE
2. The range of ac-to-dc ratio across different users
3. Signal current changes expected from artifacts (such as motion and ambient light changes)
4. The SNR required for heart-rate extraction algorithms to function successfully

Based on the above analysis, the available dynamic range from the AFE (approximately 100 dB) can be partitioned between the various components, and the target dc level for the calibration algorithm can also be arrived at.

9.2.2.2 Reducing Sensitivity to Ambient Light Modulation

Ambient light has an additive effect to the LED phase output of the AFE because ambient light occurs on the photodiode in a manner similar to the light originating from the LED. Any artifacts in ambient light can therefore interfere with the extraction of the heart rate from the signal in the LED phase. The purpose of subtracting the ambient phase signal from the LED phase signal is to remove this effect. If the effect of ambient light on the LED and ambient phase outputs is unequal, then subtraction of the ambient phase data from the LED phase data gives only an incomplete cancellation of the ambient light modulation effect. In that case, a periodic pattern in the ambient light can cause spurious tones to appear in the (LED-Ambient) data. The following guidelines can significantly reduce the sensitivity of the AFE to ambient light modulation:

• Follow the timing guidelines listed in Table 7.
• t₁ (the start of the LED to the start of sampling) plays a role in the sensitivity to ambient light modulation. For best performance under high ambient light modulation, keeping t₁ to a value greater than 25 µs is recommended even when operating at low sampling pulse durations.
• The TIA maintains the photodiode bias through negative feedback. If the TIA output saturates, then the photodiode bias is disturbed. The associated transient for the photodiode bias to get restored can increase the sensitivity to ambient light modulation. For example, a saturation of the TIA output during the LED3 phase can lead to the TIA recovery response to span both the LED1 and Ambient1 phases. This scenario can cause the channel response to differ between these two phases, thereby rendering the ambient subtraction through (LED1-Ambient1) to be incomplete. Therefore, the output of every phase is recommended to be prevented from saturating (through periodic signal monitoring and gain adjustment) even if the data from that phase is not being used by the heart rate estimation algorithm.
• If the ambient light changes at a fast rate, the effective ambient signal observed during the LED and ambient phases can be different because of the difference between the sampling instants. This effect can also cause the ambient subtraction to be incomplete. Reducing the spacing between the sampling instants of the LED and ambient can reduce this effect.

Figure 93 is the AFE output in the ambient phase resulting from modulation applied to the ambient light. Figure 94 is the (LED-Ambient) phase data with non-optimal settings and Figure 95 is the (LED-Ambient) phase data with optimal settings.

Figure 93. Ambient Data with Ambient Light Modulation

Figure 95. (LED-Ambient) Data with an Optimal AFE Setting

Figure 94. (LED-Ambient) Data with a Non-Optimal AFE Setting

9.2.3 Application Curves

This section outlines the trends described in the Typical Characteristics section from an application perspective.

Figure 1 illustrates the receiver current across different external clock frequencies. Each of the curves corresponds to a different CLKDIV_EXTMODE setting that determines the division ratio between the external clock and the internal clock (CLK_INT). The internal clock frequency must be in the range of 4 MHz to 6 MHz for proper operation, and each curve corresponds to a sweep of the external clock frequency that corresponds to an internal clock frequency sweep over the range of 4 MHz to 6 MHz.

Figure 2 illustrates the receiver current across the PRF with the dynamic power-down signal (PDN_CYCLE) enabled during the portion of the period when the receiver does not need to be active. The active period is maintained as 500 µs for each PRF setting and the device is in power-down mode (set by PDN_CYCLE) for the rest of the period. Additionally, the timing margins indicated as t₈ and t₉ in Figure 35 are included before and after the PDN_CYCLE pulse. The fraction of time that the device is in power-down mode over a period increases with reduction in the PRF because the period scales inversely with PRF. This timing is the reason why the curve displays a reduction in the average receiver current with reduction in PRF. The curve corresponding to CLKDIV_PRF = 1 terminates at a lower PRF of approximately 61 Hz, which is determined by the maximum range of the 16-bit timing counter (4 MHz divided by 2¹⁶). With the CLKDIV_PRF set to 16, the timer clock is divided by 16. Thus, the lower PRF range can be extended down to a few hertz (the recommended operation is to restrict the range to 10 Hz or higher). For the same PRF (for example 100 Hz), a higher CLKDIV_PRF setting results in a lower power consumption because the timer engine runs on a slower clock and takes less switching current.

The noise plots from Figure 3 to Figure 7 are taken at a PRF of 100 Hz. For this PRF setting, the noise at the output of the AFE is distributed from 0 Hz to 50 Hz. Plots that indicate the noise as over Nyquist bandwidth have integrated noise from 1 Hz to 50 Hz. The plots that indicate the noise as over 20-Hz bandwidth have integrated noise until 20 Hz. These plots are suitable for when additional low-pass filtering is implemented in the MCU to limit the noise bandwidth (in this case, to 20 Hz). This low-pass filtering can improve SNR because the PPG signal has information contained in the frequency band below 10 Hz.

Figure 3 illustrates the input-referred noise current versus sampling duration duty cycle for different voltage levels at the receiver output. The PPG signal has a dc component that can cause the signal at the output of the receiver to be anywhere between ±FS (full-scale). The curves in Figure 3 illustrate a slight increase in the noise around higher dc levels, which results from additional noise sources in the ADC. The input-referred noise current can be visualized as a noise current flowing into one of the input pins (for instance, INP) and flowing out of the other (for example, INM). The noise is computed on the samples that constitute the difference between the LED phase and the ambient phase.

Figure 4 illustrates the SNR plots corresponding to the same data as Figure 3. The input-referred noise and SNR can be related as follows: the input-referred noise current can be first referred to the receiver output using a factor of 2R_f, where R_f is 500 kΩ for this case. This output-referred voltage gives the output noise that can then be referred to the full-scale value of 2 V (note that when the full-scale differential input to the ADC is 2.4 V_PP, the operating range is 2 V_PP, which is the valid operating range of the TIA).

Figure 5 plots the input-referred noise current versus sampling duty cycle across different TIA gain settings.

Figure 6 corresponds to the SNR plot of the data in Figure 5. As illustrated in Figure 5, a dynamic range of 100 dB or more can be achieved in the receiver for many of the TIA gain settings. A reduction in SNR for higher TIA gain settings is in line with what is expected from the receiver because a higher TIA gain setting implies a lower signal level at the input of the receiver.

Figure 7 and Figure 8 correspond to the input-referred noise current and corresponding SNR across the sampling duration duty cycle for different settings of the ADC averaging (as set by the NUMAV register setting). An ADC averaging of 1 implies no averaging. As illustrated in these curves, the SNR improves with averaging more samples. This improvement becomes more pronounced at lower TIA gain settings where the ADC noise has a higher affect on the overall receiver noise.

The input-referred current noise current versus sampling duty cycle for different decimation factors is illustrated in Figure 9. As illustrated in Figure 9, a 4X decimation leads to almost a 2X reduction in input-referred noise.

Figure 10 refers to a hypothetical case that is used to illustrate the improvement in the receiver dynamic range when using the offset cancellation DAC. Assume that the dc level of the signal current corresponds to 7.25 µA. Without the offset cancellation DAC, assume operation is with a TIA gain of 25 kΩ, which causes the output of the receiver to be at 362.5 mV. If the offset cancellation DAC is enabled with a subtraction current of 7 µA (the maximum setting), then the signal level at the input of the TIA after the offset cancellation DAC subtraction is 0.25 µA. For this current, a TIA gain setting of 1 MΩ causes the TIA output to be at 500 mV. In effect, by enabling the offset cancellation DAC with the right setting, a higher TIA gain setting is allowed, which ends up reducing the contribution of the ADC noise and thereby reduces the input-referred noise current of the receiver. Note that the benefit from the offset cancellation DAC may not be so dramatic in an actual use case because perfect cancellation of the dc signal may not be achieved from the 0.5-µA resolution of the offset cancellation DAC. Even if achieved, the highest possible TIA gain setting on the residual current may cause receiver saturation with small changes in the dc signal level. For this reason, a safe value for the maximum gain setting when operating with the offset cancellation DAC is 250 kΩ or less. The third curve in Figure 10 illustrates this case.

Figure 11 illustrates the effective response of the switched RC filter at the receiver output. The switched RC filter has a physical RC time constant that corresponds to a bandwidth of approximately 2.5 kHz. However, the effective bandwidth of the filter scales approximately with the sampling duration duty cycle. For a lower duty cycle, the effective filter bandwidth reduces as described from the comparison of a 5% duty cycle with a 25% duty cycle. At even lower duty cycles, the filter can double-up as a noise bandwidth reduction filter that can relax the digital-filtering requirements in the MCU.

Figure 12 illustrates the switched RC filter response for a sampling duty cycle of 1% across different PRF settings.

Figure 13 illustrates the switched RC filter response for a sampling duty cycle of 5% across different PRF settings.

Figure 14 illustrates the LED current value versus the LED current setting code. The mode marked as 50-mA LED Current Mode corresponds to the default setting of ILED_2X = 0, whereas the mode marked as 100-mA LED Current Mode corresponds to ILED_2X = 1. The ideal slope of these curves corresponds to 0.793 mA per code for the 50-mA current mode and 1.587 mA per code for the 100-mA current mode. However, a small deviation from these ideal values can exist from device to device, and can be viewed as a gain error in the LED current versus code. This deviation can be larger for the 100-mA current mode, with slight saturation of current especially at the high-current settings.

Figure 15 illustrates the LED current as a function of the voltage at the TX pin. The voltage at the TX pin is changed by connecting a load resistor from the TX pin to TX_SUP and changing the voltage of TX_SUP. In the 50-mA current mode, with a 50-mA current setting, the LED current starts to drop when the voltage at the TX pin goes below 0.5 V. In the 100-mA current mode, with a 100-mA current setting, the current starts to drop when the voltage at the TX pin goes below 1 V.

Figure 16 and Figure 17 illustrate the LED current step error as a function of the LED current setting code for the 50-mA and 100-mA current modes. These plots are generated from the data in Figure 14 after removing the gain error component (based on the best-fit curve).

Figure 18 illustrates the power-supply rejection ratio (PSRR) for a tone on the TX_SUP power rail. The frequency of the tone is swept and the magnitude of the same tone at the device output (LED-ambient) is monitored. Note that in cases where the tone frequency is greater than PRF / 2, power is monitored at the aliasing frequency. PSRR is computed as the RMS value of the output tone referred to the RMS value of the tone applied on the supply pin.

Figure 19 illustrates the PSRR for a tone applied on the RX_SUP power rail. PSRR is enhanced because of the presence of an internal LDO that drives the signal chain as well as the differential nature of the signal chain.

Figure 20 illustrates the rejection of a 50-Hz differential input tone. A differential current input with a frequency of 50 Hz is applied on the input pins. The magnitude of the tone at the output of the device (LED minus ambient phase) is converted to an input-referred current and compared with the magnitude of the injected current to estimate the rejection. The rejection is plotted as a function of the separation between the sampling instants of the LED and ambient phases. As illustrated in Figure 20, with reducing separation between the sampling instants, the rejection keeps improving because of an increased correlation of the injected tone between the two phases. A similar rejection is not obtained if only the LED phase data are considered.

Figure 21 illustrates the SNR in dBFS over a 20-Hz bandwidth across sampling duty cycle over multiple operating temperatures ranging from –40°C to 85°C.

Figure 22 illustrates the variation of the internal oscillator frequency over operating temperature on a typical unit.