SLASFA1 july   2023 AFE539F1-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: ADC Input
    6. 6.6  Electrical Characteristics: General
    7. 6.7  Timing Requirements: I2C Standard Mode
    8. 6.8  Timing Requirements: I2C Fast Mode
    9. 6.9  Timing Requirements: I2C Fast Mode Plus
    10. 6.10 Timing Requirements: SPI Write Operation
    11. 6.11 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    12. 6.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    13. 6.13 Timing Requirements: PWM Output
    14. 6.14 Timing Diagrams
    15. 6.15 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Analog Front End (AFE) Architecture
      2. 7.3.2 Programming Interface
      3. 7.3.3 Nonvolatile Memory (NVM)
        1. 7.3.3.1 NVM Cyclic Redundancy Check (CRC)
          1. 7.3.3.1.1 NVM-CRC-FAIL-USER Bit
          2. 7.3.3.1.2 NVM-CRC-FAIL-INT Bit
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 External Reset
      6. 7.3.6 Register-Map Lock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Analog-to-Digital Converter (ADC) Mode
        1. 7.4.1.1 Voltage Reference Selection
          1. 7.4.1.1.1 Power-Supply as Reference
          2. 7.4.1.1.2 Internal Reference
          3. 7.4.1.1.3 External Reference
      2. 7.4.2 Pulse-Width Modulation (PWM) Mode
      3. 7.4.3 Constant Power-Dissipation Control
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  REF-GAIN-CONFIG Register (address = 15h) [reset = 0401h]
      3. 7.6.3  COMMON-CONFIG Register (address = 1Fh) [reset = 13FFh]
      4. 7.6.4  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      5. 7.6.5  COMMON-PWM-TRIG Register (address = 21h) [reset = 0001h]
      6. 7.6.6  GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      7. 7.6.7  INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      8. 7.6.8  STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      9. 7.6.9  SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      10. 7.6.10 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      11. 7.6.11 MAX-OUTPUT Register (SRAM address = 20h) [reset = 007Fh]
      12. 7.6.12 MIN-OUTPUT Register (SRAM address = 21h) [reset = 0000h]
      13. 7.6.13 FUNCTION-COEFFICIENT Register (SRAM address = 22h) [reset = 01F4h]
      14. 7.6.14 PWM-FREQUENCY Register (SRAM address = 23h) [reset = 000Bh]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.15 Typical Characteristics

at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, and gain = 1 × (unless otherwise noted)

GUID-20230627-SS0I-1TCR-FMRX-7XSSRMZ1D0TQ-low.svg
 
Figure 6-4 ADC INL vs Digital Output Code
GUID-20230627-SS0I-RH1L-BHSK-LXJHSSNWKVPR-low.svg
 
Figure 6-6 ADC DNL vs Digital Output Code
GUID-20230627-SS0I-SLV5-D27S-NSMKNSND1HRF-low.svg
 
Figure 6-8 ADC Offset Error vs Temperature
GUID-20230627-SS0I-J4VQ-11GV-LVBPSMJKC59C-low.svg
 
Figure 6-10 ADC Gain Error vs Temperature
GUID-20220410-SS0I-XK34-PRCF-R7VXD3TMMHVF-low.svg
Internal reference
Figure 6-12 Internal Reference vs Temperature
GUID-20220410-SS0I-6MSL-X9XZ-KKBV0XWF76QJ-low.svg
Sleep mode, internal reference disabled
Figure 6-14 Power-Down Current vs Temperature
GUID-20230627-SS0I-QQ4V-367T-NXJPQWGGVHWK-low.svg
 
Figure 6-5 ADC INL vs Temperature
GUID-20230627-SS0I-01KT-0KP7-H3R9SCWW5WXX-low.svg
 
Figure 6-7 ADC DNL vs Temperature
GUID-20230627-SS0I-5WDB-7FWQ-ZHGMKWKG0TWJ-low.svg
 
Figure 6-9 ADC Gain Error vs Digital Output Code
GUID-20230627-SS0I-ZBDN-TKJW-V2QKGBSR1WHB-low.svg
Input at mid scale
Figure 6-11 ADC Count vs Digital Output Code
GUID-20220410-SS0I-NV8K-LMKN-RFM0FSKSQRKK-low.svg
Internal reference
Figure 6-13 Internal Reference vs Supply Voltage
GUID-20220410-SS0I-P0TL-ZGLV-JWZ8GJZRSB3X-low.svg
 
Figure 6-15 Boot-Up Time vs Capacitance on CAP pin