SLASFA1 july   2023 AFE539F1-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: ADC Input
    6. 6.6  Electrical Characteristics: General
    7. 6.7  Timing Requirements: I2C Standard Mode
    8. 6.8  Timing Requirements: I2C Fast Mode
    9. 6.9  Timing Requirements: I2C Fast Mode Plus
    10. 6.10 Timing Requirements: SPI Write Operation
    11. 6.11 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    12. 6.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    13. 6.13 Timing Requirements: PWM Output
    14. 6.14 Timing Diagrams
    15. 6.15 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Analog Front End (AFE) Architecture
      2. 7.3.2 Programming Interface
      3. 7.3.3 Nonvolatile Memory (NVM)
        1. 7.3.3.1 NVM Cyclic Redundancy Check (CRC)
          1. 7.3.3.1.1 NVM-CRC-FAIL-USER Bit
          2. 7.3.3.1.2 NVM-CRC-FAIL-INT Bit
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 External Reset
      6. 7.3.6 Register-Map Lock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Analog-to-Digital Converter (ADC) Mode
        1. 7.4.1.1 Voltage Reference Selection
          1. 7.4.1.1.1 Power-Supply as Reference
          2. 7.4.1.1.2 Internal Reference
          3. 7.4.1.1.3 External Reference
      2. 7.4.2 Pulse-Width Modulation (PWM) Mode
      3. 7.4.3 Constant Power-Dissipation Control
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  REF-GAIN-CONFIG Register (address = 15h) [reset = 0401h]
      3. 7.6.3  COMMON-CONFIG Register (address = 1Fh) [reset = 13FFh]
      4. 7.6.4  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      5. 7.6.5  COMMON-PWM-TRIG Register (address = 21h) [reset = 0001h]
      6. 7.6.6  GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      7. 7.6.7  INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      8. 7.6.8  STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      9. 7.6.9  SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      10. 7.6.10 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      11. 7.6.11 MAX-OUTPUT Register (SRAM address = 20h) [reset = 007Fh]
      12. 7.6.12 MIN-OUTPUT Register (SRAM address = 21h) [reset = 0000h]
      13. 7.6.13 FUNCTION-COEFFICIENT Register (SRAM address = 22h) [reset = 01F4h]
      14. 7.6.14 PWM-FREQUENCY Register (SRAM address = 23h) [reset = 000Bh]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3 Nonvolatile Memory (NVM)

The AFE539F1-Q1 contain nonvolatile memory (NVM) bits. These memory bits are user programmable and erasable, and retain set values in the absence of a power supply. The highlighted gray cells in the Register Map show all the register bits that can be stored in the NVM by setting NVM-PROG = 1 in the COMMON-TRIGGER register. The NVM-PROG bit autoresets. The NVM-BUSY bit in the GENERAL-STATUS register is set to 1 by the device when an NVM write or reload operation is ongoing. During this time, the device blocks all read and write operations from and to the device. The NVM-BUSY bit is set to 0 after the write or reload operation is complete; at this point, all read and write operations from and to the device are allowed. The default value for all the registers in the AFE539F1-Q1 is loaded from NVM as soon as a POR event is issued.

The AFE539F1-Q1 also implements a NVM-RELOAD bit in the COMMON-TRIGGER register. Set this bit to 1 for the device to start an NVM-reload operation. The NVM-reload operation overwrites the register map with the stored data from the NVM. After completion, the device autoresets this bit to 0. During the NVM-RELOAD operation, the NVM-BUSY bit is set to 1.