SLOS729D October   2011  – November 2015 AFE5808A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Digital Characteristics
    7. 7.7  Switching Characteristics
    8. 7.8  Timing Requirements
    9. 7.9  Output Interface Timing
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Low-Noise Amplifier (LNA)
      2. 8.3.2 Voltage-Controlled Attenuator
      3. 8.3.3 Programmable Gain Amplifier
      4. 8.3.4 Analog-to-Digital Converter
      5. 8.3.5 Continuous-Wave (CW) Beamformer
        1. 8.3.5.1 16 × ƒcw Mode
        2. 8.3.5.2 8 × ƒcw and 4 × ƒcw Modes
        3. 8.3.5.3 1 × ƒcw Mode
      6. 8.3.6 Equivalent Circuits
      7. 8.3.7 LVDS Output Interface Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 TGC Mode
      2. 8.4.2 CW Mode
      3. 8.4.3 TGC + CW Mode
      4. 8.4.4 Test Modes
        1. 8.4.4.1 ADC Test Modes
        2. 8.4.4.2 VCA Test Mode
      5. 8.4.5 Power Management
        1. 8.4.5.1 Power and Performance Optimization
        2. 8.4.5.2 Power Management Priority
        3. 8.4.5.3 Partial Power Up and Power Down Mode
        4. 8.4.5.4 Complete Power-Down Mode
        5. 8.4.5.5 Power Saving in CW Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Register Timing
        1. 8.5.1.1 Serial Register Write Description
        2. 8.5.1.2 Register Readout Description
    6. 8.6 Register Maps
      1. 8.6.1 ADC Register Map
      2. 8.6.2 ADC Register/Digital Processing Description
        1. 8.6.2.1  AVERAGING_ENABLE: Address: 2[11]
        2. 8.6.2.2  ADC_OUTPUT_FORMAT: Address: 4[3]
        3. 8.6.2.3  DIGITAL_GAIN_ENABLE: Address: 3[12]
        4. 8.6.2.4  DIGITAL_HPF_ENABLE
        5. 8.6.2.5  DIGITAL_HPF_FILTER_K_CHX
        6. 8.6.2.6  LOW_FREQUENCY_NOISE_SUPPRESSION: Address: 1[11]
        7. 8.6.2.7  LVDS_OUTPUT_RATE_2X: Address: 1[14]
        8. 8.6.2.8  CHANNEL_OFFSET_SUBSTRACTION_ENABLE: Address: 3[8]
        9. 8.6.2.9  SERIALIZED_DATA_RATE: Address: 3[14:13]
        10. 8.6.2.10 TEST_PATTERN_MODES: Address: 2[15:13]
        11. 8.6.2.11 SYNC_PATTERN: Address: 10[8]
      3. 8.6.3 VCA Register Map
      4. 8.6.4 AFE5808A VCA Register Description
        1. 8.6.4.1 LNA Input Impedances Configuration (Active Termination Programmability)
        2. 8.6.4.2 Programmable Gain for CW Summing Amplifier
        3. 8.6.4.3 Programmable Phase Delay for CW Mixer
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 LNA Configuration
          1. 9.2.2.1.1 LNA Input Coupling and Decoupling
          2. 9.2.2.1.2 LNA Noise Contribution
          3. 9.2.2.1.3 Active Termination
          4. 9.2.2.1.4 LNA Gain Switch Response
        2. 9.2.2.2 Voltage-Controlled-Attenuator
        3. 9.2.2.3 CW Operation
          1. 9.2.2.3.1 CW Summing Amplifier
          2. 9.2.2.3.2 CW Clock Selection
          3. 9.2.2.3.3 CW Supporting Circuits
        4. 9.2.2.4 ADC Operation
          1. 9.2.2.4.1 ADC Clock Configurations
          2. 9.2.2.4.2 ADC Reference Circuit
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
      1. 9.3.1 Driving the Inputs (Analog or Digital) Beyond the Power-Supply Rails
      2. 9.3.2 Driving the Device Signal Input With an Excessively High Level Signal
      3. 9.3.3 Driving the VCNTL Signal With an Excessive Noise Source
      4. 9.3.4 Using a Clock Source With Excessive Jitter, an Excessively Long Input Clock Signal Trace, or Having Other Signals Coupled to the ADC or CW Clock Signal Trace
      5. 9.3.5 LVDS Routing Length Mismatch
      6. 9.3.6 Failure to Provide Adequate Heat Removal
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from C Revision (January 2014) to D Revision

  • Added Device Information and ESD Ratings tables, and Detailed Description, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections.Go
  • Updated Pin Diagram. Go
  • Deleted Packaging/Ordering Information tableGo
  • Updated ESD values to ±1000 (HBM) and ±250 (CDM). Go
  • Updated ω0t+22.5⁰ to ω0t-22.5⁰ in Equation 2 Go
  • Updated t+1/16f0 to t-1/16f0 in Equation 3 Go
  • Added Application Companion Devices table. Go
  • Added Figure 85. Go

Changes from B Revision (April 2012) to C Revision

  • Changed pin description of CLKM_16X from "In the 1X CW clock mode, this pin becomes the quadrature-phase 1X CLKM for the CW mixer" to "... in-phase 1X CLKM for the CW mixer"Go
  • Changed pin description of CLKP_16X from "In the 1X CW clock mode, this pin becomes the quadrature-phase 1X CLKP for the CW mixer" to "... in-phase 1X CLKP for the CW mixer"Go
  • Changed pin description of CLKM_1X from "In the 1X CW clock mode, this pin becomes the in-phase 1X CLKP for the CW mixer" to "... quadrature-phase 1X CLKP for the CW mixer"Go
  • Changed pin description of CLKP_1X from "In the 1X CW clock mode, this pin becomes the in-phase 1X CLKP for the CW mixer" to "... quadrature-phase 1X CLKP for the CW mixer"Go
  • Added min and max columns to Absolute Maximum Ratings tableGo
  • Changed CLK duty cycle from "35%~65%" to "33% to 66%"Go
  • Changed 5V 1% duty cycle current from 16.5 mA to 26 mA.Go
  • Deleted "In the 16X operation mode, the CW operation range is limited to 8 MHz due to the 16X CLK. The maximum clock frequency for the 16X CLK is 128 MHz. " in the footnote for CW Operation Range Go
  • Added "After January, 2014, that is date code after 41XXXXX, the CW Clock frequency ( 16X mode) can be supported up to 145 MHz and approximately 33 to 50% duty cycle based on additional test screening."Go
  • Changed Input Clock to Bit Clock and deleted "(for output data and frame clock)"Go
  • Changed Input Clock to Bit Clock and deleted "(for output data and frame clock)"Go
  • Added a note "The above timing data can be applied to 12-bit or 16-bit LVDS rates"Go
  • Added "The maximum PGA output level can be above 2 VPP even with the clamp circuit enabled" in the PGA description.Go
  • Changed "10 Ω" to "approximately 10- to 15-Ω " in Figure 64Go
  • Updated Figure 67Go
  • Updated Figure 69Go
  • Changed SPI pull down resistors from "100 kΩ" to "20 kΩ".Go
  • Corrected a typo in Reg0x2[15:13], i.e. changed 0x2[15:3] to 0x2[15:13]Go
  • Added Reg0x32[10] PGA_CLAMP_-6dB. Go
  • Added a note " 0x32[10] needs to be set as 0" in the Reg0x33[7:5] description. Go
  • Combined Reg 0x33[6:5] and 0x33[7] and added notes to PGA_CLAMP_LEVEL: "The maximum PGA output level can exceed 2 VPP with the clamp circuit enabled. In the low power and medium power modes, PGA_CLAMP is disabled for saving power if 51[7] = 0". Go
  • Added Note: 54[9] is only effective in CW mode. Go
  • Added and reorganized Description of LNA Input Impedances ConfigurationGo
  • Added Table 9Go
  • Added text "TI recommends that VCNTLM/P noise is below 25 nV/√Hz at 1 kHz and 5 nV/√Hz at 50 kHz. In high channel count premium systems, the VCNTLM/P noise requirement is higher." Go
  • Added a note "The local oscillator inputs of the passive mixer are cos(ωt) for I-CH and sin(ωt) for Q-CH " Go
  • Added LMK048X into the CW clock application information section. Go
  • Updated Figure 89 to include LMK devices.Go
  • Updated Figure 90 to include LMK devicesGo
  • Added LMK048X into the ADC clock application information section. Go
  • Deleted "VREF_IN" from "The AFE5808A has a number of reference supplies needed to be bypassed."Go
  • Added "To avoid noise coupling through supply pins, TI recommends to keep sensitive input pins, such as INM, INP, ACT pins aways from the AVDD 3.3 V and AVDD_5V planes. For example, either the traces or vias connected to these pins should NOT be routed across the AVDD 3.3 V and AVDD_5V planes, that is to avoid power planes under INM, INP, and ACT pins." in Layout GuidelinesGo

Changes from A Revision (November 2011) to B Revision

  • Added pin compatible device AFE5803 to the Description textGo
  • Changed the PIN FUNCTIONS DescriptionsGo
  • Changed the tdelay Test Condiitons From: Input clock rising edge (zero cross) to frame clock rising edge (zero cross) minus half the input clock period (T). To: Input clock rising edge (zero cross) to frame clock rising edge (zero cross) minus 3/7 of the input clock period (T).Go
  • Added Note: "In the low power and medium power modes, PGA_CLAMP is disabled for saving power if 51[7] = 0."Go
  • Changed Figure 64Go
  • Changed the CHANNEL_OFFSET_SUBSTRACTION_ENABLE: Address: 3[8] textGo
  • Added Note: 59[8] is only effective in TGC test mode.Go
  • Changed Figure 81Go

Changes from * Revision (October 2011) to A Revision

  • Changed CW signal carrier freq From 8 MHz Max To 8 MHz typicalGo
  • Changed CW Clock freq, 4X CLK From 32 MHz Max To 32 MHz typicalGo
  • Moved footnote "Low Noise Mode/Medium Power Mode/Low Power Mode" to the test condition for Input Referred Current NoiseGo
  • Added footnote for CW Operation RangeGo
  • Added text to the Power Management Priority sectionGo
  • Added text to the ADC Register Map sectionGo
  • Added text to the CW Clock Selection sectionGo