SLASEU7 March   2023 AFE781H1 , AFE881H1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Timing Diagrams
    8. 6.8  Typical Characteristics: VOUT DAC
    9. 6.9  Typical Characteristics: ADC
    10. 6.10 Typical Characteristics: Reference
    11. 6.11 Typical Characteristics: HART Modem
    12. 6.12 Typical Characteristics: Power Supply
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter (DAC) Overview
        1. 7.3.1.1 DAC Resistor String
        2. 7.3.1.2 DAC Buffer Amplifier
        3. 7.3.1.3 DAC Transfer Function
        4. 7.3.1.4 DAC Gain and Offset Calibration
        5. 7.3.1.5 Programmable Slew Rate
        6. 7.3.1.6 DAC Register Structure and CLEAR State
      2. 7.3.2 Analog-to-Digital Converter (ADC) Overview
        1. 7.3.2.1 ADC Operation
        2. 7.3.2.2 ADC Custom Channel Sequencer
        3. 7.3.2.3 ADC Synchronization
        4. 7.3.2.4 ADC Offset Calibration
        5. 7.3.2.5 External Monitoring Inputs
        6. 7.3.2.6 Temperature Sensor
        7. 7.3.2.7 Self-Diagnostic Multiplexer
        8. 7.3.2.8 ADC Bypass
      3. 7.3.3 Programmable Out-of-Range Alarms
        1. 7.3.3.1 Alarm-Based Interrupts
        2. 7.3.3.2 Alarm Action Configuration Register
        3. 7.3.3.3 Alarm Voltage Generator
        4. 7.3.3.4 Temperature Sensor Alarm Function
        5. 7.3.3.5 Internal Reference Alarm Function
        6. 7.3.3.6 ADC Alarm Function
        7. 7.3.3.7 Fault Detection
      4. 7.3.4 IRQ
      5. 7.3.5 HART Interface
        1. 7.3.5.1  FIFO Buffers
          1. 7.3.5.1.1 FIFO Buffer Access
          2. 7.3.5.1.2 FIFO Buffer Flags
        2. 7.3.5.2  HART Modulator
        3. 7.3.5.3  HART Demodulator
        4. 7.3.5.4  HART Modem Modes
          1. 7.3.5.4.1 Half-Duplex Mode
          2. 7.3.5.4.2 Full-Duplex Mode
        5. 7.3.5.5  HART Modulation and Demodulation Arbitration
          1. 7.3.5.5.1 HART Receive Mode
          2. 7.3.5.5.2 HART Transmit Mode
        6. 7.3.5.6  HART Modulator Timing and Preamble Requirements
        7. 7.3.5.7  HART Demodulator Timing and Preamble Requirements
        8. 7.3.5.8  IRQ Configuration for HART Communication
        9. 7.3.5.9  HART Communication Using the SPI
        10. 7.3.5.10 HART Communication Using UART
        11. 7.3.5.11 Memory Built-In Self-Test (MBIST)
      6. 7.3.6 Internal Reference
      7. 7.3.7 Integrated Precision Oscillator
      8. 7.3.8 One-Time Programmable (OTP) Memory
    4. 7.4 Device Functional Modes
      1. 7.4.1 DAC Power-Down Mode
      2. 7.4.2 Reset
    5. 7.5 Programming
      1. 7.5.1 Communication Setup
        1. 7.5.1.1 SPI Mode
        2. 7.5.1.2 UART Mode
        3. 7.5.1.3 SPI Plus UART Mode
        4. 7.5.1.4 HART Functionality Setup Options
      2. 7.5.2 Serial Peripheral Interface (SPI)
        1. 7.5.2.1 SPI Frame Definition
        2. 7.5.2.2 SPI Read and Write
        3. 7.5.2.3 Frame Error Checking
        4. 7.5.2.4 Synchronization
      3. 7.5.3 UART Interface
        1. 7.5.3.1 UART Break Mode (UBM)
          1. 7.5.3.1.1 Interface With FIFO Buffers and Register Map
      4. 7.5.4 Status Bits
      5. 7.5.5 Watchdog Timer
    6. 7.6 Register Maps
      1. 7.6.1 AFEx81H1 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Multichannel Configuration
    2. 8.2 Typical Application
      1. 8.2.1 4-mA to 20-mA Current Transmitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Start-Up Circuit
          2. 8.2.1.2.2 Current Loop Control
          3. 8.2.1.2.3 Input Protection and Rectification
          4. 8.2.1.2.4 System Current Budget
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
8.2.1.2.2 Current Loop Control

The AFE881H1 sets an output voltage from 0.3 V to 2.5 V if configured in Range 0 with PVDD > 2.7 V. Figure 8-5 shows the feedback circuit that sets the loop current from the DAC output voltage.

Figure 8-5 Current Loop Control for the AFE881H1 Transmitter

In this circuit, the VOUT voltage is set across 100 kΩ of resistance (from the 11.3 kΩ plus 88.7 kΩ of series resistance) by the AFE881H1. The opposite end of the 100 kΩ of resistance is set to ground by the feedback of the OPA333. The current across the 100-kΩ resistance is VOUT divided by 100 kΩ. This current continues through the 40.2-kΩ resistor so that the voltage at LOOP– is less than ground. Equation 11 calculates the voltage at LOOP–.

Equation 11. V   L O O P – =   – V O U T   /   100   k Ω ×   40.2   k Ω   =   – V O U T   ×   0.402

When the DAC output voltage is set to 0.3 V, the voltage at LOOP– is 0.1206 V less than ground. When the DAC output voltage is set to 2.5 V, the voltage at LOOP– is 1.005 V less than ground. The LOOP– voltage sets the loop current that flows from ground to LOOP– through the 40.2-Ω resistor. This current is sourced from ground but controlled by the current sunk from Q4 coming from the start-up circuit. Equation 12 calculates the loop current.

Equation 12. I   L O O P =   – V L O O P   /   40.2   k Ω

Substituting Equation 12 into Equation 11, Equation 13 is obtained.

Equation 13. I   L O O P =   V O U T × 0.402   /   40.2   Ω = V O U T   /   100   Ω

When the DAC output voltage is set to 0.3 V, the loop current is 3 mA. When the DAC output voltage is set to 2.5 V, the loop current is 25 mA. The OPA333 drives the base of transistor Q4 to pull the correct amount of current to set the feedback loop. The current pulled from LOOP+ powers the board. Excess current greater than what is required to power the board is shunted through the TLVH431B regulator.

The AFE881H1 sets the DAC output voltage through an output code. This conversion to output voltage is set through Equation 1; VMIN = 0.3 V and FSR = 2.2 V, resulting in Equation 14.

Equation 14. V O U T = D A C _ C O D E 2 16 × 2.2   V + 0.3   V

In 4-mA to 20-mA systems, the nominal output operates from 4 mA as the low output and 20 mA as the high output. However, systems sometimes use current outputs that are outside this range to indicate different error conditions. Loop currents of 3.375 mA and 21.75 mA can be used to indicate different loop errors. Table 8-1 shows different loop output currents, along with the DAC code and voltages used.

Table 8-1 DAC Voltage Output and Loop Current Based on DAC Output Codes
OUTPUT CONDITION DAC CODE DAC OUTPUT (V) LOOP CURRENT (mA)
DAC minimum 0x0000 0.3 3
Error low 0x045D 0.3375 3.375
In-range minimum 0x0BA2 0.4 4
In-range midscale 0x68BA 1.2 12
In-range maximum 0xC5D1 2.0 20
Error high 0xDA2E 2.175 21.75
DAC maximum 0xFFFF 2.5 25

Among the passive devices included in the design, choose gain-setting resistors that exhibit tight tolerances to achieve high accuracy. These resistors are primarily responsible for setting the gain of the current loop, along with primary path of the output current flow.

Similar to converting the VOUT pin voltage to the loop current magnitude, the HART output from the MOD_OUT pin is converted from a voltage to a current. A dc-blocking capacitor of 1000 pF is used to couple in the HART signal without the dc output offset from the MOD_OUT pin. From MOD_OUT, the HART sinusoid nominal output is 500 mVpp. Equation 15 shows that this VMOD HART sinusoid voltage is set across a 499-kΩ resistor to create signal voltage VLOOPAC superimposed onto VLOOP–.

Equation 15. V L O O P A C   =   V M O D   /   499   k Ω ×   40.2   k Ω   = V M O D   ×   0.08056

The VLOOPAC voltage sets the HART-modulated loop current that flows from ground to LOOP– through the 40.2-Ω resistor. This current is sourced from ground but controlled by the current sunk from Q4 coming from the start-up circuit. Equation 16 calculates the loop current.

Equation 16. I L O O P A C   =   V L O O P A C     /   4 0 . 2    k Ω  

Substituting Equation 15 into Equation 16, Equation 17 is obtained.

Equation 17. I L O O P A C   =   V M O D × 0 . 0 8 0 5 6 / 4 0 . 2   Ω   = 5 0 0   m V p p × 0 . 0 8 0 5 6 / 4 0 . 2   Ω   =   1   m A p p  

Using the 1000-pF capacitor as a dc-blocking capacitor and the 499-kΩ resistor, the 500-mVpp MOD_OUT signal is converted to a 1-mApp HART signal on the current loop.