AIN0 |
15 |
AI |
ADC input voltage. The input range is 0 V to VREF if PVDD = VDD, or
0 V to 2 × VREF if PVDD > 2.7 V. |
ALARM |
24 |
DO |
Alarm notification. Open drain. When alarm condition is asserted,
this pin is held to logic low; otherwise, this pin is in a
high-impedance state (Hi-Z). |
CD |
3 |
DO |
Carrier detect. A logic high on this pin indicates a valid carrier
is present. |
CLK_OUT |
11 |
DO |
Clock output. This pin can be configured as a clock output for the
1.2288‑MHz internal clock. |
CS |
10 |
DI |
SPI chip-select. Data bits are clocked into the serial shift
register when CS is logic low. When
CS is logic high, SDO is in a
high-impedance state and data on SDI are ignored. Do not leave any
digital input pins floating. |
GND |
14 |
P |
Digital and analog ground. Ground reference point for all circuitry
on the device. |
IOVDD |
12 |
P |
Interface supply. Supply voltage for digital input and output
circuitry. This voltage sets the logical thresholds for the digital
interfaces. |
MOD_OUT |
23 |
AO |
FSK output sinusoid. Maximum supported parallel load capacitance is
2 nF. |
POL_SEL/AIN1 |
16 |
DI/AI |
ADC input voltage if SPECIAL_CFG.AIN1_ENB bit is set to 1. The
input range is 0 V to VREF if PVDD = VDD, or 0 V to 2 × VREF if PVDD
> 2.7 V. Otherwise, this pin acts as ALMV_POL, which sets the
polarity of the VOUT alarm voltage. |
PVDD |
17 |
P |
Power supply for the internal low-dropout regulator (LDO), ADC
input, and VOUT DAC output. When 2.7 V to 5.5 V is provided, the
internal LDO turns on and drives VDD internally. When 1.71 V to
1.89 V is provided, the internal LDO is disabled. |
REF_EN |
5 |
DI |
Internal VREF enable input. A logic high on this pin enables the
internal VREF and the VREFIO pin outputs 1.25 V. A logic low on this
pin disables the internal VREF and the external 1.25-V reference is
required at the VREFIO pin. |
REF_GND |
20 |
P |
GND reference for VREFIO pin. |
RESET |
6 |
DI |
Reset. Logic low on this pin places the device into power-down mode
and resets the device. Logic high returns the device to normal
operation. Do not leave any digital input pins floating. |
RTS |
4 |
DI |
Request to send. A logic high on this pin enables the demodulator
and disables the modulator. A logic low on this pin enables the
modulator and disables the demodulator. Do not leave any digital
input pins floating. |
RX_IN |
21 |
AI |
HART FSK input if no external filter is used; otherwise, do not
connect any signal to this pin. |
RX_INF |
22 |
AI |
HART FSK input if using the external band-pass filter. If using the
internal band-pass filter by connecting the HART FSK to RX_IN, then
connect a 680-pF capacitor to this pin. |
SCLK |
7 |
DI |
SPI serial clock. Data can be transferred at rates up to 12.5 MHz.
SCLK is a Schmitt-trigger logic input. Connect to GND or logic low
if not used. Do not leave any digital input pins floating. |
SDI |
8 |
DI |
SPI data input. Data are clocked into the 24‑bit input shift
register on the falling edge of the serial clock input. SDI is a
Schmitt-Trigger logic input. Do not leave any digital input pins
floating. |
SDO |
9 |
DO |
SPI data output. Data are output on the rising edge of SCLK when
CS is logic low. Interrupt request (IRQ)
pin in the UART break mode (UBM). The output is in a Hi-Z state at
power up and must be enabled in the CONFIG register. |
UARTIN |
1 |
DI |
UART data input. Connect to IOVDD or logic high if not used. Do not
leave any digital input pins floating. |
UARTOUT |
2 |
DO |
UART data output. This pin can be configured to function as the IRQ
pin in SPI only mode. |
VDD |
13 |
P/AO |
Power supply. When 2.7 V to 5.5 V is provided on PVDD pin, the
internal LDO drives VDD internally. Connect a 1‑μF to 10‑μF
capacitor to this pin. When 1.71 V to 1.89 V is provided on the PVDD
pin, an external power supply must be provided on this pin. |
VOUT |
18 |
AO |
DAC output voltage. |
VREFIO |
19 |
AI/AO |
When the internal VREF is enabled by REF_EN pin, this pin outputs
the internal VREF voltage. In this case, a load capacitance of 70-nF
to 130-nF is required for stability. When disabled, this pin is the
external 1.25‑V reference input. |