SBASAF7C january   2022  – may 2023 AFE7906

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Description (continued)
  6. 5Revision History
  7. 6Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  RF ADC Electrical Characteristics
    6. 6.6  PLL/VCO/Clock Electrical Characteristics
    7. 6.7  Digital Electrical Characteristics
    8. 6.8  Power Supply Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
      1. 6.11.1 RX Typical Characteristics 30 MHz and 400 MHz
      2. 6.11.2 RX Typical Characteristics at 800MHz
      3. 6.11.3 RX Typical Characteristics 1.75GHz to 1.9GHz
      4. 6.11.4 RX Typical Characteristics 2.6GHz
      5. 6.11.5 RX Typical Characteristics 3.5GHz
      6. 6.11.6 RX Typical Characteristics 4.9GHz
      7. 6.11.7 RX Typical Characteristics 6.8GHz
      8. 6.11.8 PLL and Clock Typical Characteristics
  8. 7Device and Documentation Support
    1. 7.1 Receiving Notification of Documentation Updates
    2. 7.2 Support Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary
  9. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Description (continued)

Each receiver chain includes a 25-dB range DSA (Digital Step Attenuator), followed by a 3-GSPS ADC (analog-to-digital converter). Each receiver channel has an analog peak power detector and various digital power detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for device reliability protection. Flexible decimation options provide optimization of data bandwidth up to 1200 MHz for four RX without FB paths or 600 MHz with two FB paths (1200 MHz BW each).

The device contains a SYSREF timing detector to allow optimization of the SYSREF input timing relative to the device clock.