SBASAF7C january   2022  – may 2023 AFE7906

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Description (continued)
  6. 5Revision History
  7. 6Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  RF ADC Electrical Characteristics
    6. 6.6  PLL/VCO/Clock Electrical Characteristics
    7. 6.7  Digital Electrical Characteristics
    8. 6.8  Power Supply Electrical Characteristics
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
      1. 6.11.1 RX Typical Characteristics 30 MHz and 400 MHz
      2. 6.11.2 RX Typical Characteristics at 800MHz
      3. 6.11.3 RX Typical Characteristics 1.75GHz to 1.9GHz
      4. 6.11.4 RX Typical Characteristics 2.6GHz
      5. 6.11.5 RX Typical Characteristics 3.5GHz
      6. 6.11.6 RX Typical Characteristics 4.9GHz
      7. 6.11.7 RX Typical Characteristics 6.8GHz
      8. 6.11.8 PLL and Clock Typical Characteristics
  8. 7Device and Documentation Support
    1. 7.1 Receiving Notification of Documentation Updates
    2. 7.2 Support Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary
  9. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Digital Electrical Characteristics

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CML SerDes Outputs [8:1]STX+/-
FSerDes SerDes Bit Rate Full rate mode 19 29.5 Gbps
Half rate mode 9.5 16.25
Quarter rate mode 4.75 8.125
1/8th rate mode 2.375 4.062
1/16th rate mode 1.1875 2.031
TJ Total Jitter Tolerance 0.42 UI
VSTDIFF SerDes Transmitter Output Amplitude differential 500 1000 mVpp
VSTCOM SerDes Output Common Mode 0.4 0.45 0.55 V
ZSTdiff SerDes Output Impedance 100 Ω
TRF Output rise and fall time 20-80% 8 ps
TTJ Output total jitter 0.21 UI
CMOS I/O: GPIO{B/C/D/E}x, SPICLK, SPISDIO, SPISDO, SPISEN, RESETZ, BISTB0, BISTB1
VIH High-Level Input Voltage 0.6×VDD1P8GPIO V
VIL Low-Level Input Voltage 0.4×VDD1P8GPIO V
IIH High-Level Input Current –250 250 µA
IIL Low-Level Input Current –250 250 µA
CL CMOS input capacitance 2 pF
VOH High-Level Output Voltage VDD1P8GPIO–0.2 V
VOL Low-Level Output Voltage 0.2 V
Differential Inputs: SYSREF+/- Mode A
FSYSREFMAX SYSREF Input Frequency Maximum 40 MHz
VSWINGSRMAX SYSREF Input Swing Maximum 1.8 Vppdiff(2)
VSWINGSRMIN SYSREF Input Swing Minimum fREF < 500MHz 0.3 Vppdiff(2)
VSWINGSRMIN SYSREF Input Swing Minimum fREF > 500MHz 0.6 Vppdiff(2)
VCOMSRMAX SYSREF Input Common Mode Voltage Maximum 0.8 V
VCOMSRMIN SYSREF Input Common Mode Voltage Minimum 0.6 V
ZT Input termination differential 100 (1) Ω
CL Input capacitance Each pin to GND 0.5 pF
LVDS Inputs: 0SYNCIN+/- and 1SYNCIN+/-
VICOM Input Common Voltage 1.2 V
VID Differential Input Voltage swing 450 Vppdiff(2)
ZT Input termination differential 100 Ω
LVDS Outputs: 0SYNCOUT+/- and 1SYNCOUT+/-
VOCOM Output Common Voltage 1.2 V
VOD Differential Output Voltage swing 500 Vppdiff(2)
ZT Internal Termination 100 Ω
(1) SYSREF termination is programmable between 100Ω, 150Ω and 300Ω
(2) Vppdiff is the difference between the maximum differential voltage (positive value) and minimum differential voltage (negative value).