Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated
Including PCB and cable losses, Aout = -0.5dBFS, DSA = 0, 2.6GHz matching |
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Figure 4-78 TX Full Scale vs RF Frequency at 11796.48MSPSfDAC = 8847.36MSPS, straight mode, matching at 2.6GHz |
Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1 |
Figure 4-80 TX Uncalibrated Differential Gain Error vs DSA Setting and Channel at 2.6GHzfDAC = 8847.36MSPS, straight mode, matching at 2.6GHz |
Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting) |
Figure 4-82 TX Uncalibrated Integrated Gain Error vs DSA Setting and Channel at 2.6GHzfDAC = 8847.36MSPS, straight mode,
matching at 2.6GHz, channel with the median variation
over DSA setting at 25°C |
Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1 |
Figure 4-84 TX Uncalibrated Differential Gain Error vs DSA Setting and Temperature at 2.6GHzfDAC = 8847.36MSPS, straight mode,
matching at 2.6GHz, channel with the median variation
over DSA setting at 25°C |
Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting) |
Figure 4-86 TX Uncalibrated Integrated Gain Error vs DSA Setting and Temperature at 2.6GHzfDAC = 8847.36MSPS, straight mode,
matching at 2.6GHz |
Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) |
|
Figure 4-88 TX Uncalibrated Differential Phase Error vs DSA Setting and Channel at 2.6GHzfDAC = 8847.36MSPS, straight mode,
matching at 2.6GHz |
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0) |
Figure 4-90 TX Uncalibrated Integrated Phase Error vs DSA Setting and Channel at 2.6GHzfDAC = 8847.36MSPS, straight mode,
matching at 2.6GHz, channel with the median variation
over DSA setting at 25°C |
Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) |
Figure 4-92 TX Uncalibrated Differential Phase Error vs DSA Setting and Temperature at 2.6GHzfDAC = 8847.36MSPS, straight mode,
matching at 2.6GHz, channel with the medium variation
over DSA setting at 25°C |
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0) |
Figure 4-94 TX Uncalibrated Integrated Phase Error vs DSA Setting and Temperature at 2.6GHzfDAC = 8847.36MSPS, straight mode,
matching at 2.6GHz, POUT = –13 dBFS |
Figure 4-96 TX Output Noise vs Channel and Attenuation at 2.6GHzfDAC = 8847.36MSPS, straight mode,
fCENTER = 2.6GHz, matching at 2.6GHz, –13
dBFS each tone |
Figure 4-98 TX IMD3 vs Tone Spacing and Channel at 2.6GHzfDAC = 8847.36MSPS, straight mode,
fCENTER = 2.6GHz, fSPACING =
20 MHz, matching at 2.6GHz |
Figure 4-100 TX IMD3 vs Digital Level at 2.6GHzMatching at 2.6GHz, Single tone, fDAC = 11.79648GSPS, interleave mode, 40-MHz offset |
Figure 4-102 TX Single Tone Output Noise vs Frequency and Amplitude at 2.6GHzMatching at 2.6GHz, single carrier 20MHz BW
TM1.1 LTE |
Figure 4-104 TX 20-MHz LTE ACPR vs Digital Level at 2.6GHzMatching at 2.6GHz, single carrier 20MHz BW
TM1.1 LTE |
Figure 4-106 TX 20-MHz LTE ACPR vs DSA at 2.6GHzMatching at 2.6GHz, single carrier 20MHz BW
TM1.1 LTE |
Figure 4-108 TX 20-MHz LTE ACPR vs DSA at 2.6GHzMatching at 2.6GHz, single carrier 100MHz BW
TM1.1 NR |
Figure 4-110 TX 100-MHz NR ACPR vs DSA at 2.6GHzMatching at 2.6GHz, fDAC =
11.79648GSPS, interleave mode, normalized to output
power at harmonic frequency |
Figure 4-112 TX HD2 vs Digital Amplitude and Output Frequency at 2.6GHzfDAC = 8847.36MSPS, straight mode,
2.6GHz matching, includes PCB and cable losses. ILn =
fS/n ± fOUT and is due to
mixing with digital clocks. |
Figure 4-114 TX Single Tone (–12dBFS)
Output Spectrum at 2.6GHz (0-fDAC)fDAC = 8847.36MSPS, straight mode,
2.6GHz matching, includes PCB and cable losses. ILn =
fS/n ± fOUT and is due to
mixing with digital clocks. |
Figure 4-116 TX Single Tone (–1dBFS)
Output Spectrum at 2.6GHz (0-fDAC)fDAC = 8847.36MSPS, Aout = -0.5dBFS, matching 2.6GHz |
|
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Figure 4-79 TX Output Power vs DSA Setting and Channel at 2.6GHzfDAC = 8847.36MSPS, straight mode, matching at 2.6GHz |
Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1 |
Figure 4-81 TX Calibrated Differential Gain Error vs DSA Setting and Channel at 2.6GHzfDAC = 8847.36MSPS, straight mode,
matching at 2.6GHz |
Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting) |
|
Figure 4-83 TX Calibrated Integrated Gain Error vs DSA Setting and Channel at 2.6GHzfDAC = 8847.36MSPS, straight mode,
matching at 2.6GHz, channel with the median variation
over DSA setting at 25°C |
Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1 |
Figure 4-85 TX Calibrated Differential Gain Error vs DSA Setting and Temperature at 2.6GHzfDAC = 8847.36MSPS, straight mode,
matching at 2.6GHz, channel with the median variation
over DSA setting at 25°C |
Integrated Gain Error = POUT(DSA Setting) – POUT(DSA Setting = 0) + (DSA Setting) |
Figure 4-87 TX Calibrated Integrated Gain Error vs DSA Setting and Temperature at 2.6GHzfDAC = 8847.36MSPS, straight mode,
matching at 2.6GHz |
Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) |
Phase DNL spike may occur at any DSA setting. |
Figure 4-89 TX Calibrated Differential Phase Error vs DSA Setting and Channel at 2.6GHzfDAC = 8847.36MSPS, straight mode,
matching at 2.6GHz |
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0) |
|
Figure 4-91 TX Calibrated Integrated Phase Error vs DSA Setting and Channel at 2.6GHzfDAC = 8847.36MSPS, straight mode,
matching at 2.6GHz, channel with the median variation
over DSA setting at 25°C |
Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) |
Figure 4-93 TX Calibrated Differential Phase Error vs DSA Setting and Temperature at 2.6GHzfDAC = 8847.36MSPS, straight mode,
matching at 2.6GHz, channel with the median variation
over DSA setting at 25°C |
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0) |
Figure 4-95 TX Calibrated Integrated Phase Error vs DSA Setting and Temperature at 2.6GHzfDAC = 8847.36MSPS, straight mode,
fCENTER = 2.6GHz, matching at 2.6GHz, –13
dBFS each tone |
Figure 4-97 TX IMD3 vs DSA Setting at 2.6GHzfDAC = 8847.36MSPS, straight mode,
fCENTER = 2.6GHz, matching at 2.6GHz, –13
dBFS each tone, worst channel. |
Figure 4-99 TX IMD3 vs Tone Spacing and Temperature at 2.6GHzfDAC = 8847.36MSPS, straight mode,
fCENTER = 2.6GHz, matching at 2.6GHz, –13
dBFS each tone |
Figure 4-101 TX IMD3 vs Tone Spacing and TemperatureTM1.1, POUT_RMS = –13dBFS |
Figure 4-103 TX 20-MHz LTE Output Spectrum at 2.6GHz (Band 41)Matching at 2.6GHz, single carrier 20MHz BW
TM1.1 LTE |
Figure 4-105 TX 20-MHz LTE alt-ACPR vs Digital Level at 2.6GHzMatching at 2.6GHz, single carrier 20MHz BW
TM1.1 LTE |
Figure 4-107 TX 20-MHz LTE alt-ACPR vs DSA at 2.6GHzMatching at 2.6GHz, single carrier 20MHz BW
TM1.1 LTE |
Figure 4-109 TX 20-MHz LTE alt-ACPR vs DSA at 2.6GHzMatching at 2.6GHz, single carrier 100MHz BW
TM1.1 NR |
|
Figure 4-111 TX 100-MHz NR alt-ACPR vs DSA at 2.6GHzMatching at 2.6GHz, fDAC =
11.79648GSPS, interleave mode, normalized to output
power at harmonic frequency |
Figure 4-113 TX HD3 vs Digital Amplitude and Output Frequency at 2.6GHzfDAC = 8847.36MSPS, straight mode,
2.6GHz matching, includes PCB and cable losses. ILn =
fS/n ± fOUT and is due to
mixing with digital clocks. |
Figure 4-115 TX Single Tone (–6dBFS)
Output Spectrum at 2.6GHz (0-fDAC)fDAC = 11796.48MSPS, interleave
mode, 2.6GHz matching. 40MHz offset from tone. Output
Power = –13dBFS. All supplies simultaneously at MIN,
TYP, or MAX voltages. |
Figure 4-117 TX IMD3 vs Supply Voltage at 2.6GHz