SBASAG7A March   2024  – August 2024 AFE7950-SP

PRODMIX  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Transmitter Electrical Characteristics
    6. 4.6  RF ADC Electrical Characteristics
    7. 4.7  PLL/VCO/Clock Electrical Characteristics
    8. 4.8  Digital Electrical Characteristics
    9. 4.9  Power Supply Electrical Characteristics
    10. 4.10 Timing Requirements
    11. 4.11 Switching Characteristics
    12. 4.12 Typical Characteristics
      1. 4.12.1  TX Typical Characteristics 800MHz
      2. 4.12.2  TX Typical Characteristics at 1.8GHz
      3. 4.12.3  TX Typical Characteristics at 2.6GHz
      4. 4.12.4  TX Typical Characteristics at 3.5GHz
      5. 4.12.5  TX Typical Characteristics at 4.9GHz
      6. 4.12.6  TX Typical Characteristics at 8.1GHz
      7. 4.12.7  TX Typical Characteristics at 9.6GHz
      8. 4.12.8  RX Typical Characteristics at 800MHz
      9. 4.12.9  RX Typical Characteristics at 1.75-1.9GHz
      10. 4.12.10 RX Typical Characteristics at 2.6GHz
      11. 4.12.11 RX Typical Characteristics at 3.5GHz
      12. 4.12.12 RX Typical Characteristics at 4.9GHz
      13. 4.12.13 RX Typical Characteristics at 8.1GHz
      14. 4.12.14 RX Typical Characteristics at 9.6GHz
  6. 5Device and Documentation Support
    1. 5.1 Receiving Notification of Documentation Updates
    2. 5.2 Support Resources
    3. 5.3 Trademarks
    4. 5.4 Electrostatic Discharge Caution
    5. 5.5 Glossary
  7. 6Revision History
  8. 7Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.12.11 RX Typical Characteristics at 3.5GHz

Typical values at TA = +25°C, ADC Sampling Rate = 2949.12GHz. Default conditions: output sample rate = 491.52MSPS (decimate by 6), PLL clock mode with fREF = 491.52MHz, AIN = –3dBFS, DSA setting = 4dB.

AFE7950-SP RX In-Band Gain Flatness, fIN = 3600MHz
With 3.6GHz matching, normalized to 3.6GHz
Figure 4-366 RX In-Band Gain Flatness, fIN = 3600MHz
AFE7950-SP RX Uncalibrated Differential Amplitude Error vs DSA Setting at 3.6GHz
With 3.6GHz matching
Differential Amplitude Error = PIN(DSA Setting – 1) – PIN(DSA Setting) + 1
Figure 4-368 RX Uncalibrated Differential Amplitude Error vs DSA Setting at 3.6GHz
AFE7950-SP RX Uncalibrated Integrated Amplitude Error vs DSA Setting at 3.6GHz
With 3.6GHz matching
Integrated Amplitude Error = PIN(DSA Setting) – PIN(DSA Setting = 0) + (DSA Setting)
Figure 4-370 RX Uncalibrated Integrated Amplitude Error vs DSA Setting at 3.6GHz
AFE7950-SP RX Uncalibrated Phase Error vs DSA Setting at 3.6GHz
With 3.6GHz matching
Differential Phase Error = PhaseIN(DSA Setting – 1) – PhaseIN(DSA Setting)
Figure 4-372 RX Uncalibrated Phase Error vs DSA Setting at 3.6GHz
AFE7950-SP RX Uncalibrated Integrated Phase Error vs DSA Setting at 3.6GHz
With 3.6GHz matching
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0)
Figure 4-374 RX Uncalibrated Integrated Phase Error vs DSA Setting at 3.6GHz
AFE7950-SP RX Output FFT at 3.6GHz
With 3.6GHz matching , fIN = 3610MHz, AIN = –3dBFS
Figure 4-376 RX Output FFT at 3.6GHz
AFE7950-SP RX IMD3 vs Input Level and Temperature at 3.6GHz
With 3.5GHz matching, 20MHz tone spacing
Figure 4-378 RX IMD3 vs Input Level and Temperature at 3.6GHz
AFE7950-SP RX HD2 vs DSA Setting and Temperature at 3.6GHz
With 3.5GHz matching, DDC bypass mode (TI only mode for characterization)
Figure 4-380 RX HD2 vs DSA Setting and Temperature at 3.6GHz
AFE7950-SP RX HD2 vs Input Level and Temperature at 3.6GHz
With 3.5GHz matching, DDC bypass mode (TI only mode for characterization)
Figure 4-382 RX HD2 vs Input Level and Temperature at 3.6GHz
AFE7950-SP RX HD3 vs DSA Setting and Temperature at 3.6GHz
With 3.5GHz matching, DDC bypass mode (TI only mode for characterization)
Figure 4-384 RX HD3 vs DSA Setting and Temperature at 3.6GHz
AFE7950-SP RX HD3 vs Input Level and Temperature at 3.6GHz
With 3.5GHz matching, DDC bypass mode (TI only mode for characterization)
Figure 4-386 RX HD3 vs Input Level and Temperature at 3.6GHz
AFE7950-SP RX In-Band SFDR (±200MHz) vs Input Level and Channel at 3.6GHz
With 3.5GHz matching
Figure 4-388 RX In-Band SFDR (±200MHz) vs Input Level and Channel at 3.6GHz
AFE7950-SP RX IMD3 vs Supply Voltage and Channel at 3.6GHz
With 3.6GHz matching, –7dBFS each tone, 20MHz tone spacing, all supplies at MIN, TYP, or MAX recommended operating voltages
Figure 4-390 RX IMD3 vs Supply Voltage and Channel at 3.6GHz
AFE7950-SP RX Noise Spectral Density vs Supply Voltage and Channel at 3.6GHz
With 3.6GHz matching, tone at 20 dBFS, 12.5MHz offset frequency, all supplies at MIN, TYP, or MAX recommended operating voltages
Figure 4-392 RX Noise Spectral Density vs Supply Voltage and Channel at 3.6GHz
AFE7950-SP RX Input Phase vs Temperature at 3.6GHz
With 3.6GHz matching, normalized to phase at 25°C
Figure 4-367 RX Input Phase vs Temperature at 3.6GHz
AFE7950-SP RX Calibrated Differential Amplitude Error vs DSA Setting at 3.6GHz
With 3.6GHz matching
Differential Amplitude Error = PIN(DSA Setting – 1) – PIN(DSA Setting) + 1
Figure 4-369 RX Calibrated Differential Amplitude Error vs DSA Setting at 3.6GHz
AFE7950-SP RX Calibrated Integrated Amplitude Error vs DSA Setting at 3.6GHz
With 3.6GHz matching
Integrated Amplitude Error = PIN(DSA Setting) – PIN(DSA Setting = 0) + (DSA Setting)
Figure 4-371 RX Calibrated Integrated Amplitude Error vs DSA Setting at 3.6GHz
AFE7950-SP RX Calibrated Differential Phase Error vs DSA Setting at 3.6GHz
With 3.6GHz matching
Differential Phase Error = PhaseIN(DSA Setting – 1) – PhaseIN(DSA Setting)
Figure 4-373 RX Calibrated Differential Phase Error vs DSA Setting at 3.6GHz
AFE7950-SP RX Calibrated Integrated Phase Error vs DSA Setting at 3.6GHz
With 3.6GHz matching
Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0)
Figure 4-375 RX Calibrated Integrated Phase Error vs DSA Setting at 3.6GHz
AFE7950-SP RX IMD3 vs DSA Setting and Temperature at 3.6GHz
With 3.5 GHz matching, each tone at –7dBFS, 20MHz tone spacing
Figure 4-377 RX IMD3 vs DSA Setting and Temperature at 3.6GHz
AFE7950-SP RX HD2 vs DSA Setting and Channel at 3.6GHz
With 3.5GHz matching, DDC bypass mode (TI only mode for characterization)
Figure 4-379 RX HD2 vs DSA Setting and Channel at 3.6GHz
AFE7950-SP RX HD2 vs Input Level and Channel at 3.6GHz
With 3.5GHz matching, DDC bypass mode (TI only mode for characterization)
Figure 4-381 RX HD2 vs Input Level and Channel at 3.6GHz
AFE7950-SP RX HD3 vs DSA Setting and Channel at 3.6GHz
With 3.5GHz matching, DDC bypass mode (TI only mode for characterization)
Figure 4-383 RX HD3 vs DSA Setting and Channel at 3.6GHz
AFE7950-SP RX HD3 vs Input Level and Channel at 3.6GHz
With 3.5GHz matching, DDC bypass mode (TI only mode for characterization)
Figure 4-385 RX HD3 vs Input Level and Channel at 3.6GHz
AFE7950-SP RX Noise Spectral Density vs Input Level and DSA Setting at 3.6GHz
With 3.5GHz matching, 12.5-MHz offset from tone
Figure 4-387 RX Noise Spectral Density vs Input Level and DSA Setting at 3.6GHz
AFE7950-SP RX SFDR Excluding HD2/3 vs DSA Setting and Channel at 3.6GHz
With 3.5GHz matching
Figure 4-389 RX SFDR Excluding HD2/3 vs DSA Setting and Channel at 3.6GHz
AFE7950-SP RX IMD5 vs Supply Voltage and Channel at 3.6GHz
With 3.6GHz matching, –7dBFS each tone, 20-MHz tone spacing, all supplies at MIN, TYP, or MAX recommended operating voltages
Figure 4-391 RX IMD5 vs Supply Voltage and Channel at 3.6GHz