SBASAG7A March   2024  – August 2024 AFE7950-SP

PRODMIX  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Transmitter Electrical Characteristics
    6. 4.6  RF ADC Electrical Characteristics
    7. 4.7  PLL/VCO/Clock Electrical Characteristics
    8. 4.8  Digital Electrical Characteristics
    9. 4.9  Power Supply Electrical Characteristics
    10. 4.10 Timing Requirements
    11. 4.11 Switching Characteristics
    12. 4.12 Typical Characteristics
      1. 4.12.1  TX Typical Characteristics 800MHz
      2. 4.12.2  TX Typical Characteristics at 1.8GHz
      3. 4.12.3  TX Typical Characteristics at 2.6GHz
      4. 4.12.4  TX Typical Characteristics at 3.5GHz
      5. 4.12.5  TX Typical Characteristics at 4.9GHz
      6. 4.12.6  TX Typical Characteristics at 8.1GHz
      7. 4.12.7  TX Typical Characteristics at 9.6GHz
      8. 4.12.8  RX Typical Characteristics at 800MHz
      9. 4.12.9  RX Typical Characteristics at 1.75-1.9GHz
      10. 4.12.10 RX Typical Characteristics at 2.6GHz
      11. 4.12.11 RX Typical Characteristics at 3.5GHz
      12. 4.12.12 RX Typical Characteristics at 4.9GHz
      13. 4.12.13 RX Typical Characteristics at 8.1GHz
      14. 4.12.14 RX Typical Characteristics at 9.6GHz
  6. 5Device and Documentation Support
    1. 5.1 Receiving Notification of Documentation Updates
    2. 5.2 Support Resources
    3. 5.3 Trademarks
    4. 5.4 Electrostatic Discharge Caution
    5. 5.5 Glossary
  7. 6Revision History
  8. 7Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.11 Switching Characteristics

Typical values at TA = +25°C, full temperature range is TA,MIN = -40°C to TJ,MAX = +110°C; TX Input Rate = 491.52MSPS, fDAC = 8847.36MSPS; fADC = 2949.12MSPS; nominal power supplies; 1 tone at -1 dBFS; DSA Attenuation =0dB; SerDes rate = 24.33Gbps; unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TX Channel Latency
tJESDTX JESD to TX output Latency LMFSHd=2-8-8-1, 368.64 MSPS input rate, 24x Interpolation, Serdes rate = 16.22Gbps (JESD204C) 152 interface clock cycles(1)
LMFSHd=8-16-4-1, 491.52 MSPS 24x Interpolation, Serdes rate = 16.22Gbps (JESD204C) 176
LMFSHd=4-16-8-1, 245.76 MSPS 48x Interpolation, Serdes rate = 16.22Gbps (JESD204C) 124
LMFSHd=2-16-16-1, 122.88 MSPS 96x Interpolation, Serdes rate = 16.22Gbps (JESD204C) 97
RX Channel Latency
SerDes Transmitter Analog Delay 3.6 ns
tJESDRX RX input to JESD output Latency LMFS=2-16-16-1, 122.88 MSPS, 24x Decimation, Serdes rate = 16.22Gbps (JESD204C) 92 interface clock cycles(1)
LMFS=4-16-8-1, 245.76 MSPS, 12x Decimation, Serdes rate = 16.22Gbps (JESD204C) 108
LMFS=4-8-4-1, 491.52 MSPS, 6x Decimation, Serdes rate = 16.22Gbps (JESD204C) 153
FB Channel Latency
SerDes Transmitter Analog Delay 3.6 ns
tJESDFB FB input to JESD output Latency LMFS=1-2-8-1, 368.64 MSPS, 8x Decimation 151 interface clock cycles(1)
LMFS=2-4-4-1, 491.52 MSPS, 6x Decimation 177
(1) Interface clock cycles is the period of the digital interface sample rate, e.g. 1GSPS = 1ns.