SLASEU7 Data sheet

Complex bit access types are encoded to fit into small table cells. The following table shows the codes that are used for access types in this section.

Table 7-14 AFEx81H1 Access-Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
W	WO	Write only
W	WSC	Write self clear
Reset or Default Value
-n		Value after reset or the default value
Register Array Variables
i,j,k,l,m,n		When used in a register name, an offset, or an address, these variables refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
y		When used in a register name, an offset, or an address, this variable refers to the value of a register array.

7.6.1.1 NOP Register (Offset = 0h) [Reset = 0000h]

Return to the Table 7-13.

Table 7-15 NOP Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	NOP	WO	0h	No operation. Data written to this field have no effect. Always reads zeros.

7.6.1.2 DAC_DATA Register (Offset = 1h) [Reset = 0000h]

Return to the Table 7-13.

DAC code for VOUT.

Table 7-16 DAC_DATA Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	DATA	R/W	0h	Data. DAC code for VOUT.

7.6.1.3 CONFIG Register (Offset = 2h) [Reset = 0036h]

Return to the Table 7-13.

Table 7-17 CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h
14-13	CRC_ERR_CNT	R/W	0h	CRC Errors Count Limit Sets the numbers of consecutive SPI CRC frames that must have errors before the status bits is set. 0h = 1 (default); 1h = 2; 2h = 4; 3h = 8
12	CLKO_DIV	R/W	0h	CLKO Divider Divide the clock by 128 to output to CLKO. 0h = Divider disabled, output 1.2288 MHz (default) 1h = Divider enabled, output 9600 Hz
11	CLKO_EN	R/W	0h	CLKO Enable Enable the internal oscillator to be driven on CLKO pin. 0h = Disabled (default); 1h = Enabled
10	RESERVED	R	0h
9	UBM_IRQ_EN	R/W	0h	UBM IRQ Enable Enable IRQ to be sent on UARTOUT through UBM. 0h = Disabled (default); 1h = Enabled
8	IRQ_PIN_EN	R/W	0h	IRQ Pin Enable Enable IRQ pin functionality. 0h = Disabled (default); 1h = Enabled
7	CLR_PIN_EN	R/W	0h	Clear Input Pin Enable Enable pin-based transition to the CLEAR state in UBM. 0h = Disabled (default); 1h = SDI pin configured as clear input pin
6	UART_DIS	R/W	0h	UART Disable Disable UART functionality. 0h = Disabled (default); 1h = Enabled
5	UART_BAUD	R/W	1h	UART Baud Configure BAUD rate for UART. 0h = 1200 baud (no Break) 1h = 9600 baud (Break Mode) (default)
4	CRC_EN	R/W	1h	CRC Enable Enable CRC for SPI. 0h = Disabled; 1h = Enabled (default)
3	IRQ_POL	R/W	0h	IRQ Polarity 0h = Active low (default); 1h = Active high
2	IRQ_LVL	R/W	1h	IRQ Level 0h = Edge sensitive 1h = Level sensitive (default)
1	DSDO	R/W	1h	SDO Hi-Z 0h = Drive SDO during CS = 0 1h = SDO always Hi-Z (default)
0	FSDO	R/W	0h	Fast SDO SDO is driven on negative edge of SCLK. 0h = drive SDO on rising edge of SCLK (launching edge) (default) 1h = drive SDO on falling edge of SCLK (capture edge 1/2 clock early)

7.6.1.4 DAC_CFG Register (Offset = 3h) [Reset = 0B00h]

Return to the Table 7-13.

Table 7-18 DAC_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R/W	0h
12	PD	R/W	0h	DAC Output Buffer Power-down DAC output set to Hi-Z in power-down. 0h = DAC output buffer enabled (default) 1h = DAC output buffer disabled
11-9	SR_CLK	R/W	5h	Slew Clock Rate 0h = 307.2 kHz 1h = 153.6 kHz 2h = 76.8 kHz 3h = 38.4 kHz 4h = 19.2 kHz 5h = 9600 Hz (default) 6h = 4800 Hz 7h = 2400 Hz
8-6	SR_STEP	R/W	4h	Slew Step Size 0h = 1 code 1h = 2 codes 2h = 4 codes 3h = 8 codes 4h = 16 codes (default) 5h = 32 codes 6h = 64 codes 7h = 128 codes
5	SR_EN	R/W	0h	Slew Enable Enables slew on the output voltage. 0h = Disabled (default) 1h = Enabled
4	SR_MODE	R/W	0h	Slew Mode Output slew rate mode select. 0h = Linear Slew (default) 1h = Sinusoidal Slew
3	RESERVED	R	0h
2	CLR	R/W	0h	CLEAR State 0h = Normal operation (default) 1h = Force the DAC to the CLEAR state
1	CLR_RANGE	R/W	0h	Clear Range Sets DAC CLEAR state output range. 0h = 0.15 V to 1.25 V (default) 1h = 0.2 V to 1.0 V
0	RANGE	R/W	0h	Range Sets DAC output range during normal operation. 0h = 0.15 V to 1.25 V (default) 1h = 0.2 V to 1.0 V

7.6.1.5 DAC_GAIN Register (Offset = 4h) [Reset = 8000h]

Return to the Table 7-13.

Table 7-19 DAC_GAIN Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	GAIN	R/W	8000h	Gain Set the gain of the DAC output from 0.5 – 1.499985. For example: 0000h = 0.5 8000h = 1.0 (default) FFFFh = 1.499985

Bit

Field

Type

Reset

Description

15-0

GAIN

R/W

8000h

Gain
Set the gain of the DAC output from 0.5 – 1.499985.
For example:

0000h = 0.5

8000h = 1.0 (default)

FFFFh = 1.499985

7.6.1.6 DAC_OFFSET Register (Offset = 5h) [Reset = 0000h]

Return to the Table 7-13.

Table 7-20 DAC_OFFSET Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	OFFSET	R/W	0h	Offset Adjust the offset of the DAC output, 2's complement number. For example: 0000h = 0 (default) FFFFh = –1

Bit

Field

Type

Reset

Description

15-0

OFFSET

R/W

0h

Offset
Adjust the offset of the DAC output, 2's complement number.
For example:

0000h = 0 (default)

FFFFh = –1

7.6.1.7 DAC_CLR_CODE Register (Offset = 6h) [Reset = 0000h]

Return to the Table 7-13.

Table 7-21 DAC_CLR_CODE Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	CODE	R/W	0h	CLEAR State DAC Code DAC code applied in the CLEAR state. See Section 7.3.1.6.

7.6.1.8 RESET Register (Offset = 7h) [Reset = 0000h]

Return to the Table 7-13.

Table 7-22 RESET Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h
7-0	SW_RST	WSC	0h	Software Reset Write ADh to initiate software reset.

Bit

Field

Type

Reset

Description

15-8

RESERVED

R

0h

7-0

SW_RST

WSC

0h

Software Reset

Write ADh to initiate software reset.

7.6.1.9 ADC_CFG Register (Offset = 8h) [Reset = 8810h]

Return to the Table 7-13.

Table 7-23 ADC_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	BUF_PD	R/W	1h	ADC Buffer Power-down 0h = ADC buffer enabled; 1h = ADC buffer powered down (default)
14-8	HYST	R/W	8h	Hysteresis The number of codes of hysteresis used when a threshold is exceeded for an ADC measurement of AIN0/AIN1/TEMP.
7-5	FLT_CNT	R/W	0h	Fault Count Number of successive faults to trip an alarm. Number of successive faults is programmed value + 1 (1-8 faults).
4	AIN_RANGE	R/W	1h	ADC Analog Input Range Can only be set if PVDD ≥ 2.7 V to use 2.5-V range for AIN0 and AIN1 inputs. 0h = 2 × VREF; 1h = 1 × VREF (default)
3	EOC_PER_CH	R/W	0h	ADC End-of-Conversion for Every Channel Sends an EOC pulse at the end of each channel instead of at the end of all the channels. 0h = EOC after last channel (default); 1h = EOC for every channel
2-1	CONV_RATE	R/W	0h	ADC Conversion Rate This setting only affects the conversion rate for channels AIN0 and AIN1. Rates are based on a 76.8-kHz ADC clock. All other channels use 2560 Hz. 0h = 3840 Hz (default) 1h = 2560 Hz 2h = 1280 Hz 3h = 640 Hz
0	DIRECT_MODE	R/W	0h	Direct Mode Enable 0h = Auto mode (default); 1h = Direct mode

7.6.1.10 ADC_INDEX_CFG Register (Offset = 9h) [Reset = 0080h]

Return to the Table 7-13.

The ADC custom channel sequencing configuration is shown in Table 7-24.

Table 7-24 ADC_INDEX_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	RESERVED	R	0h
7-4	STOP	R/W	8h	Custom Channel Sequencer Stop Index CCS index to stop ADC sequence. Must be ≥ START. If not, STOP is forced to = START. 0h = OFFSET 1h = AIN0 2h = AIN1 3h = TEMP 4h = SD0 (VREF) 5h = SD1 (PVDD) 6h = SD2 (VDD) 7h = SD3 (ZTAT) 8h = SD4 (VOUT) (default) 9h through Fh = GND
3-0	START	R/W	0h	Custom Channel Sequencer Start Index CCS index to start ADC sequence. 0h through Fh = Same as STOP field (0h is default)

Bit

Field

Type

Reset

Description

15-8

RESERVED

R

0h

7-4

STOP

R/W

8h

Custom Channel Sequencer Stop Index
CCS index to stop ADC sequence. Must be ≥ START. If not, STOP is forced to = START.

0h = OFFSET

1h = AIN0

2h = AIN1

3h = TEMP

4h = SD0 (VREF)

5h = SD1 (PVDD)

6h = SD2 (VDD)

7h = SD3 (ZTAT)

8h = SD4 (VOUT) (default)

9h through Fh = GND

3-0

START

R/W

0h

Custom Channel Sequencer Start Index
CCS index to start ADC sequence.

0h through Fh = Same as STOP field (0h is default)

7.6.1.11 TRIGGER Register (Offset = Ah) [Reset = 0000h]

Return to the Table 7-13.

Table 7-25 TRIGGER Register Field Descriptions

Bit	Field	Type	Reset	Description
15-3	RESERVED	R	0h
2	MBIST	WSC	0h	Memory Built-In Self-Test Trigger This trigger initiates an MBIST on the SRAM that is used for the FIFO. During this time communication to/from HART does not work as MBIST takes over the control of the SRAM.
1	SHADOWLOAD	WSC	0h	Shadowload Trigger This trigger initiates the loading of the OTP array into the parallel latches. If an OTP CRC error is detected, assert this trigger to try and reload the OTP into the memory locations.
0	ADC	WSC	0h	ADC Trigger In auto mode, this bit enables or disables the conversions. Manually set 1 (enable) and 0 (disable). In direct mode, setting this bit starts a conversion sequence. The bit is cleared at the end of the sequence. To stop a sequence prematurely, manually clear this bit.

7.6.1.12 SPECIAL_CFG Register (Offset = Bh) [Reset = 0000h]

Return to the Table 7-13.

Table 7-26 SPECIAL_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-3	RESERVED	R	0h
2	OTP_LOAD_SW_RST	R/W	0h	OTP (One Time Programmable Factory Trimmed Registers) LOAD with SW RESET OTP reloads with the assertion of a software reset (SW_RST). 0h = No reload with SW_RST 1h = Reload with SW_RST
1	ALMV_POL	R/W	0h	Alarm Voltage Polarity This register bit is ORed with the POL_SEL/AIN1 pin (if AIN1_ENB bit is low) to control the VOUT during a hardware reset condition or if alarm is active and alarm action is set appropriately. The following Boolean function is implemented for the internal signal ALMV_POL_o that sets the VOUT voltage: ALMV_POL_o = ALMV_POL OR (POL_SEL/AIN1 AND NOT AIN1_ENB) 0h = Low (0 V) 1h = High (2.5 V)
0	AIN1_ENB	R/W	0h	AIN1 Pin Enable This bit determines whether the POL_SEL/AIN1 pin acts as alarm voltage polarity control bit or an input channel to the ADC. 0h = AIN1 pin acts as alarm voltage polarity bit and ADC converts GND 1h = AIN1 pin is an active channel to the ADC

7.6.1.13 MODEM_CFG Register (Offset = Eh) [Reset = 0040h]

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Table 7-27 MODEM_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Tx2200Hz	R/W	0h	Transmit 2200 Hz Only By not sending data to the FIFO buffer and asserting RTS, the user can transmit multiples of 1200 Hz as long as RTS is asserted. By setting this bit the user can transmit multiples of 2200 Hz. Setting this bit prevents data in the FIFO buffer from being correctly transmitted. If using this bit there is no need to use the FIFO buffer. 0h = Transmit 1200 Hz and 2200 Hz (default) 1h = Transmit only 2200 Hz
14-13	RESERVED	R	0h
12	DUPLEX_EXT	R/W	0h	Duplex External Mode Allows full duplex mode but expects the connection of MOD_OUT to RX_IN to be made externally. 0h = Internal duplex connection (default) 1h = External duplex connection
11	RX_HORD_EN	R/W	0h	High Order Filter Enable Enables a higher order filter on HART_RX. 0h = Disable (default); 1h = Enable
10	RX_EXTFILT_EN	R/W	0h	External Filter Enable Enables the use of an external filter for HART_RX. If enabled, then connect the HART signal to RX_INF. 0h = Use internal filter (default); 1h = Use external filter
9	TxRES	R/W	0h	HART Transmit Resolution 0h = 32 steps per period (default) at 38.4 kHz update rate for 1200 baud 1h = 128 steps per period at 153.6 kHz update rate for 1200 baud 128-step per period waveform consumes more power.
8-4	TxAMP	R/W	4h	Transmit Amplitude HART Tx amplitude. 00h = 400 mV_PP; 01h = 425 mV_PP 02h = 450 mV_PP; 03h = 475 mV_PP 04h = 500 mV_PP (default); 05h = 525 mV_PP 06h = 550 mV_PP; 07h = 575 mV_PP 08h = 600 mV_PP; 09h = 625 mV_PP 0Ah = 650 mV_PP; 0Bh = 675 mV_PP 0Ch = 700 mV_PP; 0Dh = 725 mV_PP 0Eh = 750 mV_PP; 0Fh = 775 mV_PP 10h through 1Fh = 800 mV_PP
3	HART_EN	R/W	0h	HART Enable Enable the HART Tx and Rx. 0h = Disable (default); 1h = Enable
2	DUPLEX	R/W	0h	Duplex Mode Enable internal connection of Tx to Rx for debug and testing. 0h = Normal operation (default); 1h = Duplex enabled
1	TxHPD	R/W	0h	HART Tx DAC Output Buffer Hi-Z in Rx Mode or When Disabled 0h = HART Tx DAC output is set to midcode with 50 kΩ output impedance (default) 1h = HART Tx DAC is Hi-Z in Rx mode or when disabled. Users can set the default voltage level with an external circuit.
0	RTS	R/W	0h	Request To Send Starts transmitting a carrier on MOD_OUT pin. 0h = No action (default) 1h = Request to send. Device starts modulating the MOD_OUT pin if CD = 0.

7.6.1.14 FIFO_CFG Register (Offset = Fh) [Reset = 00F0h]

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Table 7-28 FIFO_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-10	RESERVED	R	0h
9	FIFO_H2U_FLUSH	WSC	0h	Flush HART-to-µC FIFO (FIFO_H2U) Clear the pointers for the FIFO_H2U.
8	FIFO_U2H_FLUSH	WSC	0h	Flush µC-to-HART FIFO (FIFO_U2H) Clear the pointers for the FIFO_U2H.
7-4	H2U_LEVEL_SET	R/W	Fh	FIFO_H2U FIFO Level Flag Trip Set Sets the level for FIFO_H2U at which the Level Flag trips. This is a (>) comparison. Because the FIFO size is 5 bits wide, the LSB is not used with this 4-bit setting. Only change this field while MODEM_CFG.HART_EN = 0.
3-0	U2H_LEVEL_SET	R/W	0h	FIFO_U2H FIFO Level Flag Trip Set Sets the level for FIFO_U2H at which the Level Flag trips. This is a (<) comparison. Because the FIFO size is 5 bits wide, the LSB is not used with this 4-bit setting. Only change this field while MODEM_CFG.HART_EN = 0.

7.6.1.15 ALARM_ACT Register (Offset = 10h) [Reset = 8020h]

Return to the Table 7-13.

Table 7-29 ALARM_ACT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	SD_FLT	R/W	2h	Self-Diagnostic Fault Action These bits set the device action after a self-diagnostic fault. 0h = No Action 1h = Set DAC to CLEAR state 2h = Switch to alarm voltage determined by ALMV_POL (default) 3h = Place DAC into Hi-Z (power-down)
13-12	TEMP_FLT	R/W	0h	TEMP Fault Action These bits set the device action if the ADC temperature is outside the TEMP_THRESHOLD Hi or Lo thresholds. 0h through 3h = Same as SD_FLT field (default 0h)
11-10	AIN1_FLT	R/W	0h	AIN1 Fault Action These bits set the device action if the ADC AIN1 channel is outside the AIN1_THRESHOLD Hi or Lo thresholds. 0h through 3h = Same as SD_FLT field (default 0h)
9-8	AIN0_FLT	R/W	0h	AIN0 Fault Action These bits set the device action if the ADC AIN0 channel is outside the AIN0_THRESHOLD Hi or Lo thresholds. 0h through 3h = Same as SD_FLT field (default 0h)
7-6	CRC_WDT_FLT	R/W	0h	CRC and WDT Fault Action These bits set the device action when a SPI CRC or SPI Watchdog Timeout error occurs. 0h through 3h = Same as SD_FLT field (default 0h)
5-4	VREF_FLT	R/W	2h	VREF Fault Action These bits set the device action when a fault is detected on VREF. 0h through 3h = Same as SD_FLT field a
3-2	THERM_ERR_FLT	R/W	0h	Thermal Error Fault Action These bits set the device action when a high temperature error occurs (> 130°C). 0h through 3h = Same as SD_FLT field (default 0h)
1-0	THERM_WARN_FLT	R/W	0h	Thermal Warning Fault Action These bits set the device action when a high temperature warning occurs (> 85°C). 0h through 3h = Same as SD_FLT field (default 0h)

7.6.1.16 WDT Register (Offset = 11h) [Reset = 0018h]

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Table 7-30 WDT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-6	RESERVED	R	0h
5-3	WDT_UP	R/W	3h	Watchdog Timer (WDT) Upper Limit If the WDT is enabled and the timer exceeds the programmed value, a WDT error is asserted. All times are based on 1200-Hz clock (1.2288 MHz / 1024). 0h = 53 ms (64 clocks) 1h = 106 ms (128 clocks) 2h = 427 ms (512 clocks) 3h = 853 ms (1024 clocks, default) 4h = 1.7 s (2048 clocks) 5h = 2.56 s (3072 clocks) 6h = 3.41 s (4096 clocks) 7h = 5.12 s (6144 clocks)
2-1	WDT_LO	R/W	0h	WDT Lower Limit If the WDT is enabled and the WDT Lower Limit is enabled, then only a write to this register resets the WDT timer. If the write occurs before the WDT Lower Limit time, or after the WDT Upper Limit time, then a WDT error is asserted. If WDT Lower Limit is disabled, then a write to any register resets the timer. This is true for both SPI and UART Break modes. All times are based on 1200-Hz clock (1.2288 MHz / 1024). 0h = Disabled (default) 1h = 53 ms (64 clocks) 2h = 106 ms (128 clocks) 3h = 427 ms (512 clocks)
0	WDT_EN	R/W	0h	WDT Enable 0h = Disabled (default); 1h = Enabled

7.6.1.17 AIN0_THRESHOLD Register (Offset = 12h) [Reset = FF00h]

Return to the Table 7-13.

Table 7-31 AIN0_THRESHOLD Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	Hi	R/W	FFh	High Threshold for Channel AIN0 {[11:4],4b1111} This value is compared (>) against AIN0 data bits[11:0].
7-0	Lo	R/W	0h	Low Threshold for Channel AIN0 {[11:4],4b0000} This value is compared (<) against AIN0 data bits[11:0].

7.6.1.18 AIN1_THRESHOLD Register (Offset = 13h) [Reset = FF00h]

Return to the Table 7-13.

Table 7-32 AIN1_THRESHOLD Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	Hi	R/W	FFh	High Threshold for Channel AIN1 {[11:4],4b1111} This value is compared (>) against AIN1 data bits[11:0].
7-0	Lo	R/W	0h	Low Threshold for Channel AIN1 {[11:4],4b0000} This value is compared (<) against AIN1 data bits[11:0].

7.6.1.19 TEMP_THRESHOLD Register (Offset = 14h) [Reset = FF00h]

Return to the Table 7-13.

Table 7-33 TEMP_THRESHOLD Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	Hi	R/W	FFh	High Threshold for Channel TEMP {[11:4],4b1111} This value is compared (>) against TEMP data bits[11:0].
7-0	Lo	R/W	0h	Low Threshold for Channel TEMP {[11:4],4b0000} This value is compared (<) against TEMP data bits[11:0].

7.6.1.20 FIFO_U2H_WR Register (Offset = 15h) [Reset = 0000h]

Return to the Table 7-13.

This register controls the HART to microcontroller FIFO buffer.

Table 7-34 FIFO_U2H_WR Register Field Descriptions

Bit	Field	Type	Reset	Description
15-9	RESERVED	R	0h
8	PARITY	WO	0h	Parity Odd parity bit to be transmitted with data. This field can only be written by SPI and affects the FIFO when CONFIG.UART_DIS = 1. Otherwise writes to this register are ignored.
7-0	DATA	WO	0h	Data Byte This field can only be written by SPI and affects the FIFO when CONFIG.UART_DIS = 1. Otherwise writes to this register are ignored.

7.6.1.21 UBM Register (Offset = 16h) [Reset = 0000h]

Return to the Table 7-13.

Table 7-35 UBM Register Field Descriptions

Bit	Field	Type	Reset	Description
15-1	RESERVED	R	0h
0	REG_MODE	R/W	0h	Register Mode Configure the rest of the Register Map to be accessed by UART break mode (UBM) or SPI. This register can only be written by the UART Break communication. 0h = SPI Mode (default) 1h = UART Break Mode

Bit

Field

Type

Reset

Description

15-1

RESERVED

R

0h

0

REG_MODE

R/W

0h

Register Mode
Configure the rest of the Register Map to be accessed by UART break mode (UBM) or SPI. This register can only be written by the UART Break communication.

0h = SPI Mode (default)

1h = UART Break Mode

7.6.1.22 ALARM_STATUS_MASK Register (Offset = 1Dh) [Reset = EFDFh]

Return to the Table 7-13.

Table 7-36 ALARM_STATUS_MASK Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	3h
13	SD_FLT	R/W	1h	SD Fault Mask 0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default). The status is always set if the condition exists.
12	OSC_FAIL	R/W	0h	OSC_FAIL Fault Mask Same as SD Fault Mask (default 0h).
11-9	RESERVED	R	7h
8	OTP_CRC_ERR	R/W	1h	OTP CRC Error Mask Same as SD Fault Mask (default 1h).
7	CRC_FLT	R/W	1h	SPI CRC Fault Mask Same as SD Fault Mask (default 1h).
6	WD_FLT	R/W	1h	Watchdog Fault Mask Same as SD Fault Mask (default 1h).
5	VREF_FLT	R/W	0h	VREF Fault Mask Same as SD Fault Mask (default 0h).
4	ADC_AIN1_FLT	R/W	1h	ADC AIN1 Fault Mask Same as SD Fault Mask (default 1h).
3	ADC_AIN0_FLT	R/W	1h	ADC AIN0 Fault Mask Same as SD Fault Mask (default 1h).
2	ADC_TEMP_FLT	R/W	1h	ADC TEMP Fault Mask Same as SD Fault Mask (default 1h).
1	THERM_ERR_FLT	R/W	1h	Temperature > 130°C Error Mask Same as SD Fault Mask (default 1h).
0	THERM_WARN_FLT	R/W	1h	Temperature > 85°C Warning Mask Same as SD Fault Mask (default 1h).

7.6.1.23 GEN_STATUS_MASK Register (Offset = 1Eh) [Reset = FFFFh]

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Table 7-37 GEN_STATUS_MASK Register Field Descriptions

Bit	Field	Type	Reset	Description
15-11	RESERVED	R	1Fh
10	MBIST_DONE	R/W	1h	MBIST Done Mask 0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default). The status is always set if the condition exists.
9	MBIST_FAIL	R/W	1h	MBIST Failed Fault Mask Same as MBIST Done Mask (default 1h).
8	RESERVED	R	1h
7	SR_BUSYn	R/W	1h	Slew Rate Not Busy Mask Same as MBIST Done Mask (default 1h).
6	ADC_EOC	R/W	1h	ADC End Of Conversion Mask Same as MBIST Done Mask (default 1h).
5-4	RESERVED	R	3h
3	BREAK_FRAME_ERR	R/W	1h	Break Frame Error Fault Mask Same as MBIST Done Mask (default 1h).
2	BREAK_PARITY_ERR	R/W	1h	Break Parity Error Fault Mask Same as MBIST Done Mask (default 1h).
1	UART_FRAME_ERR	R/W	1h	UART Frame Error Fault Mask Same as MBIST Done Mask (default 1h).
0	UART_PARITY_ERR	R/W	1h	UART Parity Error Fault Mask Same as MBIST Done Mask (default 1h).

7.6.1.24 MODEM_STATUS_MASK Register (Offset = 1Fh) [Reset = FFFFh]

Return to the Table 7-13.

Table 7-38 MODEM_STATUS_MASK Register Field Descriptions

Bit	Field	Type	Reset	Description
15-13	RESERVED	R	7h
12	GAP_ERR	R/W	1h	HART Gap Error Fault Mask 0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default). The status is always set if the condition exists.
11	FRAME_ERR	R/W	1h	HART Frame Error Fault Mask Same as HART Gap Error Fault Mask (default 1h).
10	PARITY_ERR	R/W	1h	HART Parity (ODD) Error Fault Mask Same as HART Gap Error Fault Mask (default 1h).
9	FIFO_H2U_LEVEL_FLAG	R/W	1h	FIFO_H2U Level Flag Mask Same as HART Gap Error Fault Mask (default 1h).
8	FIFO_H2U_FULL_FLAG	R/W	1h	FIFO_H2U Full Flag Mask Same as HART Gap Error Fault Mask (default 1h).
7	FIFO_H2U_EMPTY_FLAG	R/W	1h	FIFO_H2U Empty Flag Mask Same as HART Gap Error Fault Mask (default 1h).
6	FIFO_U2H_LEVEL_FLAG	R/W	1h	FIFO_U2H Level Flag Mask Same as HART Gap Error Fault Mask (default 1h).
5	FIFO_U2H_FULL_FLAG	R/W	1h	FIFO_U2H Full Flag Mask Same as HART Gap Error Fault Mask (default 1h).
4	FIFO_U2H_EMPTY_FLAG	R/W	1h	FIFO_U2H Empty Flag Mask Same as HART Gap Error Fault Mask (default 1h).
3	CD_DEASSERT	R/W	1h	CD Deasserted Flag Mask Same as HART Gap Error Fault Mask (default 1h).
2	CD_ASSERT	R/W	1h	CD Asserted Flag Mask Same as HART Gap Error Fault Mask (default 1h).
1	CTS_DEASSERT	R/W	1h	CTS Deasserted Flag Mask Same as HART Gap Error Fault Mask (default 1h).
0	CTS_ASSERT	R/W	1h	CTS Asserted Flag Mask Same as HART Gap Error Fault Mask (default 1h).

7.6.1.25 ALARM_STATUS Register (Offset = 20h) [Reset = 0200h]

Return to the Table 7-13.

Table 7-39 ALARM_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15	GEN_IRQ	R	0h	General IRQ OR of all the unmasked bits in the GEN_STATUS register. 0h = All of the unmasked bits of the GEN_STATUS register are low 1h = At least one of the unmasked bits in the GEN_STATUS register is high
14	MODEM_IRQ	R	0h	Modem IRQ OR of all the unmasked bits in the MODEM_STATUS register. 0h = All of the unmasked bits of the MODEM_STATUS register are low 1h = At least one of the unmasked bits in the MODEM_STATUS register is high
13	SD_FLT	R	0h	Self Diagnostic (SD) Fault 0h = All self diagnostic channels are within threshold limits 1h = At least one of the self diagnostic channels has failed
12	OSC_FAIL	R	0h	Oscillator Fault Oscillator failed to start. This bit holds ALARM low and does not feed IRQ. 0h = Oscillator started; 1h = Oscillator has failed to start
11-10	CRC_CNT	R	0h	CRC Fault Counter If counter limit ≤ 4 then bits[1:0] of the counter are shown here. If the counter limit = 8 then bits[2:1] of the counter are shown.
9	OTP_LOADEDn	R	1h	OTP NOT Loaded Clears when OTP has loaded at least once. Keeps ALARM asserted until OTP finishes loading. Does not feed IRQ. 0h = OTP has loaded at least once; 1h = OTP has not finished loading
8	OTP_CRC_ERR	R	0h	OTP CRC Error Maskable fault. An error occurred with the OTP CRC calculation. Sticky, cleared by reading register, unless condition still persist. 0h = No OTP CRC fault; 1h = OTP CRC fault
7	CRC_FLT	R	0h	CRC Fault Maskable fault. Invalid CRC value transmitted during SPI frame. Sticky, cleared by reading register, unless condition still persist. 0h = No CRC fault; 1h = CRC fault
6	WD_FLT	R	0h	Watchdog Timer Fault Maskable fault. Sticky, cleared by reading register, unless condition still persist. 0h = No watchdog fault; 1h = Watchdog fault
5	VREF_FLT	R	0h	Invalid Reference Voltage Maskable fault. OR with FORCE_FAIL.VREF_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Valid VREF voltage; 1h = Invalid VREF voltage
4	ADC_AIN1_FLT	R	0h	ADC AIN1 Fault. Maskable fault. 0h = AIN1 ADC measurement within threshold limits 1h = AIN1 ADC measurement outside threshold limits
3	ADC_AIN0_FLT	R	0h	ADC AIN0 Fault. Maskable fault. 0h = AIN0 ADC measurement within threshold limits 1h = AIN0 ADC measurement outside threshold limits
2	ADC_TEMP_FLT	R	0h	ADC Temp Fault. Maskable fault. 0h = TEMP ADC measurement within threshold limits 1h = TEMP ADC measurement outside threshold limits
1	THERM_ERR_FLT	R	0h	Temperature > 130°C error. Maskable fault. OR with FORCE_FAIL.THERM_ERR_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Temperature ≤ 130°C; 1h = Temperature > 130°C
0	THERM_WARN_FLT	R	0h	Temperature > 85°C warning. Maskable fault. OR with FORCE_FAIL.THERM_WARN_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Temperature ≤ 85°C; 1h = Temperature > 85°C

7.6.1.26 GEN_STATUS Register (Offset = 21h) [Reset = 1180h]

Return to the Table 7-13.

Table 7-40 GEN_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15	ALARM_IRQ	R	0h	Alarm IRQ OR of all the unmasked bits in the ALARM_STATUS register. 0h = All of the unmasked bits of the ALARM_STATUS register are low 1h = At least one of the unmasked bits in the ALARM_STATUS register is high
14	MODEM_IRQ	R	0h	Modem IRQ OR of all the unmasked bits in the MODEM_STATUS register. 0h = All of the unmasked bits of the MODEM_STATUS register are low 1h = At least one of the unmasked bits in the MODEM_STATUS register is high
13	RESERVED	R	0h
12	OTP_BUSY	R	1h	OTP Busy Status = 1h at power up while the OTP is being loaded into the trim latches. 0h = OTP has completed loading into the device 1h = OTP is being loaded into the device
11	RESERVED	R	0h
10	MBIST_DONE	R	0h	MBIST Completed. Maskable fault. Sticky, cleared by reading register, unless condition still persist. 0h = MBIST has not completed; 1h = MBIST has completed
9	MBIST_FAIL	R	0h	MBIST Failed. Maskable fault. Sticky, cleared by reading register, unless condition still persist. 0h = MBIST has passed; 1h = MBIST has failed
8	RESET	R	1h	Device Reset Occurred. Status only. Does not feed IRQ. Sticky, cleared by reading register, unless condition still persist. 0h = Device has not reset since last read of register 1h = Device has reset since last read of register
7	SR_BUSYn	R	1h	Slew Rate Not Busy. Maskable fault. 0h = DAC is slewing to the target code 1h = DAC_OUT has reached the DAC_DATA. If slew rate is disabled, then this signal produces a rising edge within 3 internal clock cycles. If slew rate is enabled, this signal creates an IRQ event when the DAC_OUT has reached the DAC_DATA. At this time, slew rate can be safely disabled. If slew rate is disabled prior to DAC_OUT = DAC_DATA then a jump of DAC_OUT occurs. This can cause an unwanted fast transition on VOUT.
6	ADC_EOC	R	0h	ADC End of Conversion (EOC). Maskable fault. Sticky, cleared by reading register, unless condition still persist. 0h = No EOC since last read of register; 1h = ADC end of conversion
5	ADC_BUSY	R	0h	ADC Busy. Status only. Does not feed IRQ. Active signal, set as long as condition is true. 0h = No ADC activity; 1h = ADC is actively converting
4	PVDD_HI	R	0h	PVDD High. Status only. Does not feed IRQ. Set as long as condition is true. 0h = PVDD < 2.7 V; 1h = PVDD ≥ 2.7V
3	BREAK_ FRAME_ERR	R	0h	Incorrect Stop Bit During Break Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No break frame error; 1h = Break frame error
2	BREAK_ PARITY_ERR	R	0h	Incorrect parity (ODD) bit during break character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No break parity error; 1h = Break parity error
1	UART_ FRAME_ERR	R	0h	Incorrect stop bit during UART character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No UART frame error; 1h = UART frame error
0	UART_ PARITY_ERR	R	0h	Incorrect parity (ODD) bit during UART character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No UART parity error; 1h = UART parity error

7.6.1.27 MODEM_STATUS Register (Offset = 22h) [Reset = 009Ah]

Return to the Table 7-13.

Table 7-41 MODEM_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15	ALARM_IRQ	R	0h	Alarm IRQ OR of all the unmasked bits in the ALARM_STATUS register. 0h = All of the unmasked bits of the ALARM_STATUS register are low 1h = At least one of the unmasked bits in the ALARM_STATUS register is high
14	GEN_IRQ	R	0h	General IRQ OR of all the unmasked bits in the GEN_STATUS register. 0h = All of the unmasked bits of the GEN_STATUS register are low 1h = At least one of the unmasked bits in the GEN_STATUS register is high
13	RESERVED	R	0h
12	GAP_ERR	R	0h	HART Gap Error. Maskable fault. Applies to RX_IN/RX_INF. Too much time (11 bit times) between HART characters. Sticky, cleared by reading register, unless condition still persist. Fatal Fault. 0h = No HART gap error; 1h = HART gap error
11	FRAME_ERR	R	0h	Incorrect Stop Bit in HART Character. Maskable fault. Applies to RX_IN/RX_INF. Sticky, cleared by reading register, unless condition still persist. Fatal Fault. 0h = No HART frame error; 1h = HART frame error
10	PARITY_ERR	R	0h	Incorrect Parity (ODD) Bit in HART Character. Maskable fault. Applies to RX_IN/RX_INF. Sticky, cleared by reading register, unless condition still persist. 0h = No HART parity error; 1h = HART parity error
9	FIFO_H2U_ LEVEL_FLAG	R	0h	FIFO HART-to-µC Level Flag. Maskable fault. If the level of the FIFO_H2U is full, then the level flag is not asserted, but the full flag is, so no information is lost. 0h = FIFO_H2U level ≤ {FIFO_CFG.H2U_LEVEL_SET[3:0], 1b1} 1h = FIFO_H2U level > {FIFO_CFG.H2U_LEVEL_SET[3:0], 1b1}
8	FIFO_H2U_ FULL_FLAG	R	0h	FIFO HART-to-µC Full Flag. Maskable fault. 0h = FIFO_H2U is not full; 1h = FIFO_H2U is full
7	FIFO_H2U_ EMPTY_FLAG	R	1h	FIFO HART-to-µC Empty Flag. Maskable fault. 0h = FIFO_H2U is not empty; 1h = FIFO_H2U is empty
6	FIFO_U2H_ LEVEL_FLAG	R	0h	FIFO µC-to-HART Level Flag. Maskable fault. FIFO_U2H < {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0}. When the FIFO_U2H is empty, this flag is set unless FIFO_CFG.U2H_LEVEL_SET = 0. This flag and the empty flag can be set at the same time. 0h = FIFO_U2H level ≥ {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0} 1h = FIFO_U2H level < {FIFO_CFG.U2H_LEVEL_SET[3:0], 1b0}
5	FIFO_U2H_ FULL_FLAG	R	0h	FIFO µC-to-HART Full Flag. Maskable fault. 0h = FIFO_U2H is not full; 1h = FIFO_U2H is full
4	FIFO_U2H_ EMPTY_FLAG	R	1h	FIFO µC-to-HART Empty Flag. Maskable fault. 0h = FIFO_U2H is not empty; 1h = FIFO_U2H is empty
3	CD_DEASSERT	R	1h	Carrier Detect Deasserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist. 0h = Carrier detect is asserted; 1h = Carrier detect is deasserted
2	CD_ASSERT	R	0h	Carrier Detect Asserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist. 0h = Carrier detect is deasserted; 1h = Carrier detect is asserted
1	CTS_DEASSERT	R	1h	Clear To Send Deasserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist. 0h = Clear to send is asserted; 1h = Clear to send is deasserted
0	CTS_ASSERT	R	0h	Clear To Send Asserted. Maskable fault. Sticky, cleared by reading register, unless condition still persist. 0h = Clear to send is deasserted; 1h = Clear to send is asserted

7.6.1.28 ADC_FLAGS Register (Offset = 23h) [Reset = 0000h]

Return to the Table 7-13.

The limits for Self Diagnostic (SD) Alarm ADC Thresholds are shown in Table 7-7.

Table 7-42 ADC_FLAGS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-9	RESERVED	R	0h
8	SD4_FAIL	R	0h	SD4 (VOUT) Limit Fail
7	SD3_FAIL	R	0h	SD3 (ZTAT) Limit Fail
6	SD2_FAIL	R	0h	SD2 (VDD) Limit Fail
5	SD1_FAIL	R	0h	SD1 (PVDD) Limit Fail
4	SD0_FAIL	R	0h	SD0 (VREF) Limit Fail
3	TEMP_FAIL	R	0h	TEMP Limit Fail
2	AIN1_FAIL	R	0h	AIN1 Limit Fail
1	AIN0_FAIL	R	0h	AIN0 Limit Fail
0	RESERVED	R	0h

7.6.1.29 ADC_AIN0 Register (Offset = 24h) [Reset = 0000h]

Return to the Table 7-13.

Table 7-43 ADC_AIN0 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h
11-0	DATA	R	0h	Converted Value of Voltage on Pin AIN0

7.6.1.30 ADC_AIN1 Register (Offset = 25h) [Reset = 0000h]

Return to the Table 7-13.

Table 7-44 ADC_AIN1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h
11-0	DATA	R	0h	Converted Value of Voltage on Pin AIN1

7.6.1.31 ADC_TEMP Register (Offset = 26h) [Reset = 0000h]

Return to the Table 7-13.

Table 7-45 ADC_TEMP Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h
11-0	DATA	R	0h	Converted Value of Temperature

7.6.1.32 ADC_SD_MUX Register (Offset = 27h) [Reset = 0000h]

Return to the Table 7-13.

Table 7-46 ADC_SD_MUX Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h
11-0	DATA	R	0h	Converted Value of Voltage on Self-Diagnostic (SD) MUX Input

7.6.1.33 ADC_OFFSET Register (Offset = 28h) [Reset = 0000h]

Return to the Table 7-13.

Table 7-47 ADC_OFFSET Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h
11-0	DATA	R	0h	ADC Comparator Offset This value reports the offset measured in the device, and can be used to adjust each conversion value. If ADC_BYP.OFST_BYP_EN is set, then the value in ADC_BYP.DATA is used as the offset. This value is not affected by ADC_BYP.

7.6.1.34 FIFO_H2U_RD Register (Offset = 2Ah) [Reset = 0200h]

Return to the Table 7-13.

Table 7-48 FIFO_H2U_RD Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	LEVEL	R	0h	Level Current Level of FIFO_H2U, bits [4:1] represented as Level[3:0]. Pre-dequeue.
11	LEVEL_FLAG	R	0h	HART-to-µC FIFO Level Flag Set when FIFO_H2U Level > {Level,1b1}. Pre-dequeue. 0h = FIFO_H2U level ≤ {Level, 1b1} 1h = FIFO_H2U level > {Level, 1b1}
10	FULL_FLAG	R	0h	HART-to-µC FIFO Full Flag. Pre-dequeue. 0h = FIFO_H2U is not full, pre-dequeue 1h = FIFO_H2U is full, pre-dequeue
9	EMPTY_FLAG	R	1h	HART-to-µC FIFO Empty Flag. Pre-dequeue. 0h = FIFO_H2U is not empty 1h = FIFO_H2U is empty
8	PARITY	R	0h	Parity Bit (ODD) Parity bit received with data on HART. This field can only be read by SPI when CONFIG.UART_DIS = 1. Otherwise reads from this register are ignored and do not dequeue FIFO. The default value is unknown until data are written to the FIFO.
7-0	DATA	R	0h	Data 8-bit data received on HART. This field can only be read by SPI when CONFIG.UART_DIS = 1. Otherwise reads from this register are ignored and do not dequeue FIFO. The default value is unknown until data are written to the FIFO.

7.6.1.35 FIFO_STATUS Register (Offset = 2Bh) [Reset = 0202h]

Return to the Table 7-13.

The FIFO_STATUS register is provided to allow the user to view the state of both FIFOs without enqueuing or dequeuing data in the FIFO. This also allows the flags to be viewed without disturbing other status bits in the MODEM_STATUS register. This register is provided to enable users to check the FIFO status register without disturbing other functions within the device.

Table 7-49 FIFO_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	H2U_LEVEL	R	0h	HART-to-µC FIFO Level Current level of FIFO_H2U, right shifted 1 bit (>>1) so only even counts are represented.
11	H2U_LEVEL_FLAG	R	0h	HART-to-µC FIFO Level Flag Set when FIFO Level > {Level,1b1}. 0h = FIFO_H2U level ≤ {Level, 1b1} 1h = FIFO_H2U level > {Level, 1b1}
10	H2U_FULL_FLAG	R	0h	HART-to-µC FIFO Full Flag Set when FIFO is full. 0h = FIFO_H2U is not full 1h = FIFO_H2U is full
9	H2U_EMPTY_FLAG	R	1h	HART-to-µC Empty Flag Set when FIFO is empty. 0h = FIFO_H2U is not empty 1h = FIFO_H2U is empty
8	RESERVED	R	0h
7-4	U2H_LEVEL	R	0h	µC-to-HART FIFO Level Current level of FIFO_U2H, right shifted 1 bit (>>1) so only even counts are represented
3	U2H_LEVEL_FLAG	R	0h	µC-to-HART FIFO Level Flag Set when FIFO_U2H Level < {Level,1b0}. 0h = FIFO_U2H level ≥ {Level, 1b0} 1h = FIFO_U2H level < {Level, 1b0}
2	U2H_FULL_FLAG	R	0h	µC-to-HART Full Flag Set when FIFO_U2H is full. 0h = FIFO_U2H is not full 1h = FIFO_U2H is full
1	U2H_EMPTY_FLAG	R	1h	µC-to-HART Empty Flag Set when FIFO_U2H is empty. 0h = FIFO_U2H is not empty 1h = FIFO_U2H is empty
0	RESERVED	R	0h

7.6.1.36 DAC_OUT Register (Offset = 2Ch) [Reset = 0000h]

Return to the Table 7-13.

Table 7-50 DAC_OUT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	DATA	R	0h	DAC Code Applied to the Analog Circuit

7.6.1.37 ADC_OUT Register (Offset = 2Dh) [Reset = 0000h]

Return to the Table 7-13.

Table 7-51 ADC_OUT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h
11-0	DATA	R	0h	ADC Data for Each Conversion Does not include ADC_OFFSET.DATA adjustment. Is not affected by ADC_BYP.DATA.

7.6.1.38 ADC_BYP Register (Offset = 2Eh) [Reset = 0000h]

Return to the Table 7-13.

ADC_BYP is shown in Table 7-52.

Table 7-52 ADC_BYP Register Field Descriptions

Bit	Field	Type	Reset	Description
15	DATA_BYP_EN	R/W	0h	Data Bypass Enable Applies ADC_BYP.DATA to the ADC channel being converted. ADC_OFFSET is ignored. Do not set OFST_BYP_EN and DATA_BYP_EN at the same time. If OFST_BYP_EN is also set, DATA_BYP_EN takes priority over OFST_BYP_EN. After a channel is converted, the ADC_BYP.DATA value appears in the readback register for the converted channel and is used to calculate faults. 0h = Data bypass disabled (default) 1h = Data bypass enabled
14	OFST_BYP_EN	R/W	0h	Offset Bypass Enable Overrides the offset register with the ADC_BYP.DATA value. When using this bit, the ADC_BYP.DATA field is processed as 2's complement. Do not set OFST_BYP_EN and DATA_BYP_EN at the same time. 0h = Offset bypass disabled (default) 1h = Offset bypass enabled
13	DIS_GND_SAMP	R/W	0h	Disable GND Sampling This bit disables the sampling of GND during SAR activity. The sampling of GND is used to fully discharge the sampling CAP to reduce channel crosstalk. 0h = GND sampling enabled (default) 1h = GND sampling disabled
12	RESERVED	R	0h
11-0	DATA	R/W	0h	Bypass Data

7.6.1.39 FORCE_FAIL Register (Offset = 2Fh) [Reset = 0000h]

Return to the Table 7-13.

Force failures for fault detection.

Table 7-53 FORCE_FAIL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	CRC_FLT	R/W	0h	Force CRC Failure on SDO by Inverting the CRC Byte 0h = No force failure of CRC (default) 1h = Force failure of CRC
14	VREF_FLT	R/W	0h	Force Reference Voltage Failure. Analog signal. 0h = No force failure of VREF (default) 1h = Force failure of VREF
13	THERM_ERR_FLT	R/W	0h	Force Temperature > 130°C Thermal Error. Analog signal. 0h = No force temperature > 130°C error (default) 1h = Force temperature > 130°C error
12	THERM_WARN_FLT	R/W	0h	Force Temperature > 85°C thermal Warning. Analog signal. 0h = No force temperature > 85°C warning (default) 1h = Force temperature > 85°C warning
11-10	RESERVED	R/W	0h
9	SD4_HI_FLT	R/W	0h	SD4 (VOUT) High Limit Failure. ADC measurement. 0h = No force failure of SD4 (VOUT) (default) 1h = Force failure of SD4 (VOUT)
8	SD4_LO_FLT	R/W	0h	SD4 (VOUT) Low limit failure. ADC measurement. 0h = No force failure of SD4 (VOUT) (default) 1h = Force failure of SD4 (VOUT)
7	SD3_HI_FLT	R/W	0h	SD3 (ZTAT) High Limit Failure. ADC measurement. 0h = No force failure of SD3 (ZTAT) (default) 1h = Force failure of SD3 (ZTAT)
6	SD3_LO_FLT	R/W	0h	SD3 (ZTAT) Low Limit Failure. ADC measurement. 0h = No force failure of SD3 (ZTAT) (default) 1h = Force failure of SD3 (ZTAT)
5	SD2_HI_FLT	R/W	0h	SD2 (VDD) High Limit Failure. ADC measurement. 0h = No force failure of SD2 (VDD) (default) 1h = Force failure of SD2 (VDD)
4	SD2_LO_FLT	R/W	0h	SD2 (VDD) Low Limit Failure. ADC measurement. 0h = No force failure of SD2 (VDD) (default) 1h = Force failure of SD2 (VDD)
3	SD1_HI_FLT	R/W	0h	SD1 (PVDD) High Limit Failure. ADC measurement. 0h = No force failure of SD1 (PVDD) (default) 1h = Force failure of SD1 (PVDD)
2	SD1_LO_FLT	R/W	0h	SD1 (PVDD) Low Limit Failure. ADC measurement. 0h = No force failure of SD1 (PVDD) (default) 1h = Force failure of SD1 (PVDD)
1	SD0_HI_FLT	R/W	0h	SD0 (VREF) High Limit Failure. ADC measurement. 0h = No force failure of SD0 (VREF) (default) 1h = Force failure of SD0 (VREF)
0	SD0_LO_FLT	R/W	0h	SD0 (VREF) Low Limit Failure. ADC measurement. 0h = No force failure of SD0 (VREF) (default) 1h = Force failure of SD0 (VREF)

Package Options

Mechanical Data (Package|Pins)

Thermal pad, mechanical data (Package|Pins)

Orderable Information

7.6.1 AFEx81H1 Registers

7.6.1.1 NOP Register (Offset = 0h) [Reset = 0000h]

7.6.1.2 DAC_DATA Register (Offset = 1h) [Reset = 0000h]

7.6.1.3 CONFIG Register (Offset = 2h) [Reset = 0036h]

7.6.1.4 DAC_CFG Register (Offset = 3h) [Reset = 0B00h]

7.6.1.5 DAC_GAIN Register (Offset = 4h) [Reset = 8000h]

7.6.1.6 DAC_OFFSET Register (Offset = 5h) [Reset = 0000h]

7.6.1.7 DAC_CLR_CODE Register (Offset = 6h) [Reset = 0000h]

7.6.1.8 RESET Register (Offset = 7h) [Reset = 0000h]

7.6.1.9 ADC_CFG Register (Offset = 8h) [Reset = 8810h]

7.6.1.10 ADC_INDEX_CFG Register (Offset = 9h) [Reset = 0080h]

7.6.1.11 TRIGGER Register (Offset = Ah) [Reset = 0000h]

7.6.1.12 SPECIAL_CFG Register (Offset = Bh) [Reset = 0000h]

7.6.1.13 MODEM_CFG Register (Offset = Eh) [Reset = 0040h]

7.6.1.14 FIFO_CFG Register (Offset = Fh) [Reset = 00F0h]

7.6.1.15 ALARM_ACT Register (Offset = 10h) [Reset = 8020h]

7.6.1.16 WDT Register (Offset = 11h) [Reset = 0018h]

7.6.1.17 AIN0_THRESHOLD Register (Offset = 12h) [Reset = FF00h]

7.6.1.18 AIN1_THRESHOLD Register (Offset = 13h) [Reset = FF00h]

7.6.1.19 TEMP_THRESHOLD Register (Offset = 14h) [Reset = FF00h]

7.6.1.20 FIFO_U2H_WR Register (Offset = 15h) [Reset = 0000h]

7.6.1.21 UBM Register (Offset = 16h) [Reset = 0000h]

7.6.1.22 ALARM_STATUS_MASK Register (Offset = 1Dh) [Reset = EFDFh]

7.6.1.23 GEN_STATUS_MASK Register (Offset = 1Eh) [Reset = FFFFh]

7.6.1.24 MODEM_STATUS_MASK Register (Offset = 1Fh) [Reset = FFFFh]

7.6.1.25 ALARM_STATUS Register (Offset = 20h) [Reset = 0200h]

7.6.1.26 GEN_STATUS Register (Offset = 21h) [Reset = 1180h]

7.6.1.27 MODEM_STATUS Register (Offset = 22h) [Reset = 009Ah]

7.6.1.28 ADC_FLAGS Register (Offset = 23h) [Reset = 0000h]

7.6.1.29 ADC_AIN0 Register (Offset = 24h) [Reset = 0000h]

7.6.1.30 ADC_AIN1 Register (Offset = 25h) [Reset = 0000h]

7.6.1.31 ADC_TEMP Register (Offset = 26h) [Reset = 0000h]

7.6.1.32 ADC_SD_MUX Register (Offset = 27h) [Reset = 0000h]

7.6.1.33 ADC_OFFSET Register (Offset = 28h) [Reset = 0000h]

7.6.1.34 FIFO_H2U_RD Register (Offset = 2Ah) [Reset = 0200h]

7.6.1.35 FIFO_STATUS Register (Offset = 2Bh) [Reset = 0202h]

7.6.1.36 DAC_OUT Register (Offset = 2Ch) [Reset = 0000h]

7.6.1.37 ADC_OUT Register (Offset = 2Dh) [Reset = 0000h]

7.6.1.38 ADC_BYP Register (Offset = 2Eh) [Reset = 0000h]

7.6.1.39 FORCE_FAIL Register (Offset = 2Fh) [Reset = 0000h]