SLASEU7 March   2023 AFE781H1 , AFE881H1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Timing Diagrams
    8. 6.8  Typical Characteristics: VOUT DAC
    9. 6.9  Typical Characteristics: ADC
    10. 6.10 Typical Characteristics: Reference
    11. 6.11 Typical Characteristics: HART Modem
    12. 6.12 Typical Characteristics: Power Supply
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter (DAC) Overview
        1. 7.3.1.1 DAC Resistor String
        2. 7.3.1.2 DAC Buffer Amplifier
        3. 7.3.1.3 DAC Transfer Function
        4. 7.3.1.4 DAC Gain and Offset Calibration
        5. 7.3.1.5 Programmable Slew Rate
        6. 7.3.1.6 DAC Register Structure and CLEAR State
      2. 7.3.2 Analog-to-Digital Converter (ADC) Overview
        1. 7.3.2.1 ADC Operation
        2. 7.3.2.2 ADC Custom Channel Sequencer
        3. 7.3.2.3 ADC Synchronization
        4. 7.3.2.4 ADC Offset Calibration
        5. 7.3.2.5 External Monitoring Inputs
        6. 7.3.2.6 Temperature Sensor
        7. 7.3.2.7 Self-Diagnostic Multiplexer
        8. 7.3.2.8 ADC Bypass
      3. 7.3.3 Programmable Out-of-Range Alarms
        1. 7.3.3.1 Alarm-Based Interrupts
        2. 7.3.3.2 Alarm Action Configuration Register
        3. 7.3.3.3 Alarm Voltage Generator
        4. 7.3.3.4 Temperature Sensor Alarm Function
        5. 7.3.3.5 Internal Reference Alarm Function
        6. 7.3.3.6 ADC Alarm Function
        7. 7.3.3.7 Fault Detection
      4. 7.3.4 IRQ
      5. 7.3.5 HART Interface
        1. 7.3.5.1  FIFO Buffers
          1. 7.3.5.1.1 FIFO Buffer Access
          2. 7.3.5.1.2 FIFO Buffer Flags
        2. 7.3.5.2  HART Modulator
        3. 7.3.5.3  HART Demodulator
        4. 7.3.5.4  HART Modem Modes
          1. 7.3.5.4.1 Half-Duplex Mode
          2. 7.3.5.4.2 Full-Duplex Mode
        5. 7.3.5.5  HART Modulation and Demodulation Arbitration
          1. 7.3.5.5.1 HART Receive Mode
          2. 7.3.5.5.2 HART Transmit Mode
        6. 7.3.5.6  HART Modulator Timing and Preamble Requirements
        7. 7.3.5.7  HART Demodulator Timing and Preamble Requirements
        8. 7.3.5.8  IRQ Configuration for HART Communication
        9. 7.3.5.9  HART Communication Using the SPI
        10. 7.3.5.10 HART Communication Using UART
        11. 7.3.5.11 Memory Built-In Self-Test (MBIST)
      6. 7.3.6 Internal Reference
      7. 7.3.7 Integrated Precision Oscillator
      8. 7.3.8 One-Time Programmable (OTP) Memory
    4. 7.4 Device Functional Modes
      1. 7.4.1 DAC Power-Down Mode
      2. 7.4.2 Reset
    5. 7.5 Programming
      1. 7.5.1 Communication Setup
        1. 7.5.1.1 SPI Mode
        2. 7.5.1.2 UART Mode
        3. 7.5.1.3 SPI Plus UART Mode
        4. 7.5.1.4 HART Functionality Setup Options
      2. 7.5.2 Serial Peripheral Interface (SPI)
        1. 7.5.2.1 SPI Frame Definition
        2. 7.5.2.2 SPI Read and Write
        3. 7.5.2.3 Frame Error Checking
        4. 7.5.2.4 Synchronization
      3. 7.5.3 UART Interface
        1. 7.5.3.1 UART Break Mode (UBM)
          1. 7.5.3.1.1 Interface With FIFO Buffers and Register Map
      4. 7.5.4 Status Bits
      5. 7.5.5 Watchdog Timer
    6. 7.6 Register Maps
      1. 7.6.1 AFEx81H1 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Multichannel Configuration
    2. 8.2 Typical Application
      1. 8.2.1 4-mA to 20-mA Current Transmitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Start-Up Circuit
          2. 8.2.1.2.2 Current Loop Control
          3. 8.2.1.2.3 Input Protection and Rectification
          4. 8.2.1.2.4 System Current Budget
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.5.8 IRQ Configuration for HART Communication

To enable robust and error-free communicate on the HART bus, the events listed in Table 7-9 must be detected from the AFEx81H1 by the system controller in a timely manner. If the IRQ signal is not directly connected to the system controller, poll the corresponding status flags. In UART mode, the automatic dequeue of FIFO_H2U simplifies event management significantly, and not all events must be translated to IRQs.

When using the HART modem with the IRQ, the IRQ features help control communication in both directions. Enable IRQ functionality by following these steps:

  1. Configure the IRQ to be either edge or level sensitive using CONFIG.IRQ_LVL. See also Section 7.3.4.
  2. Configure the IRQ polarity with CONFIG.IRQ_POL, as needed per the respective system. See also Section 7.3.4.
  3. For SPI only mode, set CONFIG.IRQ_PIN_EN = 1 to enable IRQ functionality on the UARTOUT pin. Also, set CONFIG.UART_DIS = 1 to disable all UART functionality.
  4. For UBM, use one of the two following methods:
    1. Set CONFIG.IRQ_PIN_EN = 1 to enable IRQ functionality on the SDO pin, or
    2. Set CONFIG.UBM_IRQ_EN = 1 to enable interrupts being sent UARTOUT using UBM.
  5. After IRQ functionality is enabled, unmask all the required interrupt signals in the MODEM_STATUS_MASK register (set each bit = 0).

Table 7-9 IRQ Sources and Uses
AFEx81H1HART STATE EVENT MODEM_STATUS FLAG ASSERTION METHOD(1) ACTION
Receive RTS deasserted CTS_DEASSERT Toggle RTS pin high or set MODEM_CFG.RTS = 0. Demodulator enabled and ready to receive HART data.
Carrier detect asserted CD_ASSERT Demodulator detects the HART carrier signal of valid amplitude. Expect to receive HART data. Set desired FIFO_H2U level trigger threshold.
FIFO_H2U level threshold trigger FIFO_H2U_LEVEL_FLAG Automatic enqueue of FIFO_H2U by HART demodulator. Dequeue data from FIFO_H2U when level exceeds the set threshold.
Prevent FIFO_H2U from being full to avoid the loss of incoming data.
FIFO_H2U full FIFO_H2U_FULL_FLAG Automatic enqueue of FIFO_H2U by HART demodulator. System controller has not dequeued FIFO_H2U. Critical flag.
Dequeue FIFO_H2U immediately to avoid the loss of incoming data.
Carrier detect deasserted CD_DEASSERT Demodulator stops detecting the HART carrier signal of valid amplitude. Dequeue remaining data from FIFO_H2U.
Monitor the empty flag to make sure that all data have been received.
FIFO_H2U empty FIFO_H2U_EMPTY_FLAG Dequeue of FIFO_H2U by system controller. If using UART, wait to make sure the last character is received on UARTOUT.
Transmit RTS asserted NA Toggle RTS pin low or write set MODEM_CFG.RTS = 1.

Wait for clear-to-send confirmation flag.
Clear to send (CTS) CTS_ASSERT RTS asserted and CD deasserted. Modulator enabled. Device starts modulating the carrier on MOD_OUT. Set desired FIFO_U2H level trigger threshold. Enqueue data into FIFO_U2H. Modulator automatically dequeues FIFO_U2H and transmits the HART data.
FIFO_U2H level threshold trigger FIFO_U2H_LEVEL_FLAG Automatic dequeue of FIFO_U2H by HART modulator. Enqueue new data into FIFO_U2H when the level drops below the set threshold.
Prevent FIFO_U2H from being empty to avoid a gap in transmission.
FIFO_U2H full FIFO_U2H_FULL_FLAG System controller enqueue of the new data into FIFO_U2H. Critical flag.
Stop enqueue of data into FIFO_U2H immediately to avoid loss of HART data.
FIFO_U2H empty FIFO_U2H_EMPTY_FLAG Automatic dequeue of FIFO_U2H by HART modulator. System controller has not enqueued new data into FIFO_U2H. Critical flag in the middle of the data packet.
Enqueue new data into FIFO_U2H immediately to avoid a gap in transmission.
When the last character is dequeued from FIFO_U2H, wait until the character is fully transmitted on MOD_OUT before deasserting RTS.
(1) For CD, RTS, ALARM, and IRQ connection choices, see Section 7.5.1.