SLASF44A May   2023  – June 2024 AFE78201 , AFE88201

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements
    7. 5.7  Timing Diagrams
    8. 5.8  Typical Characteristics: VOUT DAC
    9. 5.9  Typical Characteristics: ADC
    10. 5.10 Typical Characteristics: Reference
    11. 5.11 Typical Characteristics: Power Supply
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Digital-to-Analog Converter (DAC) Overview
        1. 6.3.1.1 DAC Resistor String
        2. 6.3.1.2 DAC Buffer Amplifier
        3. 6.3.1.3 DAC Transfer Function
        4. 6.3.1.4 DAC Gain and Offset Calibration
        5. 6.3.1.5 Programmable Slew Rate
        6. 6.3.1.6 DAC Register Structure and CLEAR State
      2. 6.3.2  Analog-to-Digital Converter (ADC) Overview
        1. 6.3.2.1 ADC Operation
        2. 6.3.2.2 ADC Custom Channel Sequencer
        3. 6.3.2.3 ADC Synchronization
        4. 6.3.2.4 ADC Offset Calibration
        5. 6.3.2.5 External Monitoring Inputs
        6. 6.3.2.6 Temperature Sensor
        7. 6.3.2.7 Self-Diagnostic Multiplexer
        8. 6.3.2.8 ADC Bypass
      3. 6.3.3  Programmable Out-of-Range Alarms
        1. 6.3.3.1 Alarm-Based Interrupts
        2. 6.3.3.2 Alarm Action Configuration Register
        3. 6.3.3.3 Alarm Voltage Generator
        4. 6.3.3.4 Temperature Sensor Alarm Function
        5. 6.3.3.5 Internal Reference Alarm Function
        6. 6.3.3.6 ADC Alarm Function
        7. 6.3.3.7 Fault Detection
      4. 6.3.4  IRQ
      5. 6.3.5  Internal Reference
      6. 6.3.6  Integrated Precision Oscillator
      7. 6.3.7  Precision Oscillator Diagnostics
      8. 6.3.8  One-Time Programmable (OTP) Memory
      9. 6.3.9  GPIO
      10. 6.3.10 Timer
      11. 6.3.11 Unique Chip Identifier (ID)
      12. 6.3.12 Scratch Pad Register
    4. 6.4 Device Functional Modes
      1. 6.4.1 Register Built-In Self-Test (RBIST)
      2. 6.4.2 DAC Power-Down Mode
      3. 6.4.3 Reset
    5. 6.5 Programming
      1. 6.5.1 Communication Setup
        1. 6.5.1.1 SPI Mode
        2. 6.5.1.2 UART Mode
      2. 6.5.2 GPIO Programming
      3. 6.5.3 Serial Peripheral Interface (SPI)
        1. 6.5.3.1 SPI Frame Definition
        2. 6.5.3.2 SPI Read and Write
        3. 6.5.3.3 Frame Error Checking
        4. 6.5.3.4 Synchronization
      4. 6.5.4 UART Interface
        1. 6.5.4.1 UART Break Mode (UBM)
      5. 6.5.5 Status Bits
      6. 6.5.6 Watchdog Timer
  8. 7 Register Maps
    1. 7.1 AFEx8201 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Multichannel Configuration
    2. 8.2 Typical Application
      1. 8.2.1 Analog Output Module
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 XTR305
            1. 8.2.1.2.1.1 Current-Output Mode
            2. 8.2.1.2.1.2 Voltage Output Mode
            3. 8.2.1.2.1.3 Diagnostic Features
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Setup
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RRU|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Register Maps

Table 7-11 lists the memory-mapped registers for the AFEx8201 registers. Consider all register offset addresses not listed in Table 7-11 as reserved locations; do not modify these register contents.

Table 7-1 Register Map
ADDR (HEX) REGISTER BIT DESCRIPTION
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00h NOP NOP [15:0]
01h DAC_DATA DATA [15:0]
02h CONFIG CRC_ERR_CNT [1:0] CLKO [3:0] UBM_
IRQ_EN		 IRQ_
PIN_EN		 CLR_
PIN_EN		 UART_DIS RESERVED CRC_EN IRQ_POL IRQ_LVL DSDO FSDO
03h DAC_CFG RESERVED PD SR_CLK [2:0] SR_STEP [2:0] SR_EN SR_MODE RESERVED CLR RESERVED
04h DAC_GAIN GAIN [15:0]
05h DAC_OFFSET OFFSET [15:0]
06h DAC_CLR_
CODE 		CODE [15:0]
07h RESET RESERVED SW_RST [7:0]
08h ADC_CFG BUF_PD HYST [6:0] FLT_CNT [2:0] AIN_
RANGE		 EOC_
PER_CH		 CONV_RATE [1:0] DIRECT_
MODE
09h ADC_INDEX_
CFG 		RESERVED STOP [3:0] START [3:0]
0Ah TRIGGER RESERVED RBIST RESERVED SHADOW
LOAD		 ADC
0Bh SPECIAL_
CFG(1)		 RESERVED OTP_
LOAD_
SW_RST		 ALMV_
POL		 AIN1_ENB
10h ALARM_ACT SD_FLT [1:0] TEMP_FLT [1:0] AIN1_FLT [1:0] AIN0_FLT [1:0] CRC_WDT_FLT [1:0] VREF_FLT [1:0] THERM_ERR_FLT [1:0] THERM_WARN_FLT [1:0]
11h WDT RESERVED WDT_UP [2:0] WDT_LO [1:0] WDT_EN
12h AIN0_
THRESHOLD 		Hi [7:0] Lo [7:0]
13h AIN1_
THRESHOLD 		Hi [7:0] Lo [7:0]
14h TEMP_
THRESHOLD 		Hi [7:0] Lo [7:0]
16h UBM(2) RESERVED REG_
MODE
18h SCRATCH DATA [15:0]
19h CHIP_ID_LSB ID [15:0]
1Ah CHIP_ID_MSB ID [15:0]
1Bh GPIO_CFG RESERVED EN [6:0] RESERVED ODE [6:0]
1Ch GPIO RESERVED DATA [6:0]
1Dh ALARM_
STATUS_MASK 		RESERVED SD_FLT OSC_FAIL RESERVED OTP_
CRC_ERR		 CRC_FLT WD_FLT VREF_FLT ADC_
AIN1_FLT		 ADC_
AIN0_FLT		 ADC_
TEMP_
FLT		 THERM_
ERR_FLT		 THERM_
WARN_
FLT
1Eh GEN_
STATUS_MASK 		RESERVED RBIST_
DONE		 RBIST_
FAIL		 RESERVED SR_
BUSYn		 ADC_
EOC		 RESERVED BREAK_
FRAME_
ERR		 BREAK_
PARITY_
ERR		 UART_
FRAME_
ERR		 UART_
PARITY_
ERR
20h ALARM_
STATUS 		GEN_
IRQ		 RESERVED SD_FLT OSC_FAIL CRC_CNT [1:0] OTP_
LOADEDn		 OTP_
CRC_ERR		 CRC_FLT WD_FLT VREF_FLT ADC_
AIN1_FLT		 ADC_
AIN0_FLT		 ADC_
TEMP_
FLT		 THERM_
ERR_FLT		 THERM_
WARN_
FLT
21h GEN_
STATUS 		ALARM_
IRQ		 RESERVED OTP_
BUSY		 RBIST_
MODE 		RBIST_
DONE		 RBIST_
FAIL		 RESET SR_
BUSYn		 ADC_
EOC		 ADC_
BUSY		 PVDD_HI BREAK_
FRAME_
ERR		 BREAK_
PARITY_
ERR		 UART
_FRAME
_ERR		 UART_
PARITY_
ERR
23h ADC_FLAGS RESERVED SD4_FAIL SD3_FAIL SD2_FAIL SD1_FAIL SD0_FAIL TEMP_
FAIL		 AIN1_
FAIL		 AIN0_
FAIL		 RESERVED
24h ADC_AIN0 RESERVED DATA [11:0]
25h ADC_AIN1 RESERVED DATA [11:0]
26h ADC_TEMP RESERVED DATA [11:0]
27h ADC_SD_MUX RESERVED DATA [11:0]
28h ADC_OFFSET RESERVED DATA [11:0]
2Ch DAC_OUT DATA [15:0]
2Dh ADC_OUT RESERVED DATA [11:0]
2Eh ADC_BYP DATA_
BYP_EN		 OFST_
BYP_EN		 DIS_GND_
SAMP		 RESERVED DATA [11:0]
2Fh FORCE_FAIL CRC_FLT VREF_FLT THERM_
ERR_FLT		 THERM_
WARN_
FLT		 RESERVED SD4_HI_
FLT		 SD4_LO_
FLT		 SD3_HI_
FLT		 SD3_LO_
FLT		 SD2_HI_
FLT		 SD2_LO_
FLT		 SD1_HI_
FLT		 SD1_LO_
FLT		 SD0_HI_
FLT		 SD0_LO_
FLT
3Bh TIMER_CFG_0 RESERVED CLK_SEL [1:0] INVERT ENABLE
3Ch TIMER_CFG_1 PERIOD [15:0]
3Dh TIMER_CFG_2 SET_TIME [15:0]
3Eh CRC_RD CRC [15:0]
3Fh RBIST_CRC CRC [15:0]
(1) The SPECIAL_CFG register can only be reset with POR, and does not respond to the RESET pin or SW_RST command.
(2) The UBM register can only be accessed with a UBM command.