SPRSPA7A September   2024  – November 2024 AM2612

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Package Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
      1. 5.1.1 AM261x ZCZ Pin Diagram
      2. 5.1.2 AM261x ZFG Pin Diagram
      3. 5.1.3 AM261x ZEJ Pin Diagram
      4. 5.1.4 AM261x ZNC Pin Diagram
    2. 5.2 Pin Attributes
      1.      15
      2.      16
    3. 5.3 Signal Descriptions
      1.      18
      2. 5.3.1  ADC
        1.       20
        2.       21
        3.       22
      3. 5.3.2  ADC_CAL
        1.       24
      4. 5.3.3  ADC VREF
        1.       26
      5. 5.3.4  CPSW
        1.       28
        2.       29
        3.       30
        4.       31
        5.       32
        6.       33
        7.       34
      6. 5.3.5  CPTS
        1.       36
      7. 5.3.6  DAC
        1.       38
      8. 5.3.7  EPWM
        1.       40
        2.       41
        3.       42
        4.       43
        5.       44
        6.       45
        7.       46
        8.       47
        9.       48
        10.       49
      9. 5.3.8  EQEP
        1.       51
        2.       52
      10. 5.3.9  FSI
        1.       54
        2.       55
      11. 5.3.10 GPIO
        1.       57
      12. 5.3.11 GPMC0
        1.       59
      13. 5.3.12 I2C
        1.       61
        2.       62
        3.       63
      14. 5.3.13 LIN
        1.       65
        2.       66
        3.       67
      15. 5.3.14 MCAN
        1.       69
        2.       70
      16. 5.3.15 SPI (MCSPI)
        1.       72
        2.       73
        3.       74
        4.       75
      17. 5.3.16 MMC
        1.       77
      18. 5.3.17 Power Supply
        1.       79
      19. 5.3.18 PRU-ICSS
        1.       81
        2.       82
        3.       83
        4.       84
        5.       85
      20. 5.3.19 OSPI
        1.       87
        2.       88
      21. 5.3.20 SDFM
        1.       90
        2.       91
      22. 5.3.21 System and Miscellaneous
        1. 5.3.21.1 Boot Mode Configuration
          1.        94
        2. 5.3.21.2 Clocking
          1.        96
          2.        97
          3.        98
        3. 5.3.21.3 Emulation and Debug
          1.        100
          2.        101
        4. 5.3.21.4 SYSTEM
          1.        103
        5. 5.3.21.5 USB0
          1.        105
        6. 5.3.21.6 VMON
          1.        107
        7.       108
          1.        109
      23. 5.3.22 UART
        1.       111
        2.       112
        3.       113
        4.       114
        5.       115
        6.       116
      24. 5.3.23 XBAR
        1.       118
        2.       119
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Electrical Characteristics
      1. 6.3.1 Digital and Analog IO Electrical Characteristics
    4. 6.4 Thermal Resistance Characteristics
      1. 6.4.1 Package Thermal Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-R5F Subsystem
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 External Oscillator
      2. 8.1.2 JTAG, EMU, and TRACE
      3. 8.1.3 Hardware Reference Design and Guidelines
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • ZFG|304
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Table 5-31 GPMC0 Signal Descriptions
Signal Name [1]Pin Type [2]Description [3]ZCZ PIN [4]ZFG PIN [4]ZEJ PIN [4]ZNC PIN [4]
GPMC0_ADVn_ALEOGPMC Address Valid (active low) or Address Latch EnableA8A10C9B9
GPMC0_CLKIOGPMC ClockL3T3M1L2
GPMC0_CLKLBIOGPMC Clock LoopbackB15A18B16A17
GPMC0_DIROGPMC Data Bus Signal Direction ControlB10D10A9
GPMC0_OEn_REnOGPMC Output Enable (active low) or Read Enable (active low)A10, B14, C8A12, A16, A9A8, B10, D13B15
GPMC0_WEnOGPMC Write Enable (active low)C14, D7B9, D17B14, B7
GPMC0_WPnOGPMC Flash Write Protect (active low)D9C9C11
GPMC0_A0OGPMC Address 0 Output. Only used to effectively address 8-bit data non-multiplexed memoriesC11B13B11C13
GPMC0_A1OGPMC Address 1 Output in A/D non-multiplexed mode and Address 17 in A/D multiplexed modeC2B1A3A3
GPMC0_A2OGPMC Address 2 Output in A/D non-multiplexed mode and Address 18 in A/D multiplexed modeD2A3C5A4
GPMC0_A3OGPMC Address 3 Output in A/D non-multiplexed mode and Address 19 in A/D multiplexed modeB2B3A4B5
GPMC0_A4OGPMC Address 4 Output in A/D non-multiplexed mode and Address 20 in A/D multiplexed modeD3A2B4A5
GPMC0_A5OGPMC Address 5 Output in A/D non-multiplexed mode and Address 21 in A/D multiplexed modeB16B19C15
GPMC0_A6OGPMC Address 6 Output in A/D non-multiplexed mode and Address 22 in A/D multiplexed modeB1C3A5A6
GPMC0_A7OGPMC Address 7 Output in A/D non-multiplexed mode and Address 23 in A/D multiplexed modeA11A13A12A12
GPMC0_A8OGPMC Address 8 Output in A/D non-multiplexed mode and Address 24 in A/D multiplexed modeA16A19C16
GPMC0_A9OGPMC Address 9 Output in A/D non-multiplexed mode and Address 25 in A/D multiplexed modeE3C2C4B2
GPMC0_A10OGPMC Address 10 Output in A/D non-multiplexed mode and Address 26 in A/D multiplexed modeD1D2B1B1
GPMC0_A11OGPMC Address 11 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeE4D1C1B3
GPMC0_A12OGPMC Address 12 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeF2E2C2C2
GPMC0_A13OGPMC Address 13 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeE2C1B2A2
GPMC0_A14OGPMC Address 14 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeC1B2A2B4
GPMC0_A15OGPMC Address 15 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeC12C14C12A14
GPMC0_A16OGPMC Address 16 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeC10B12A10B12
GPMC0_A17OGPMC Address 17 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeC15C19B17
GPMC0_A18OGPMC Address 18 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeP2U2P3T1
GPMC0_A19OGPMC Address 19 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeD15C18B16
GPMC0_A20OGPMC Address 20 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeD17, F3E19, F1F4E2
GPMC0_A21OGPMC Address 21 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeC18E20
GPMC0_AD0IOGPMC Data 0 Input/Output in A/D non-multiplexed mode and additionally Address 1 Output in A/D multiplexed modeV17W16R14V15
GPMC0_AD1IOGPMC Data 1 Input/Output in A/D non-multiplexed mode and additionally Address 2 Output in A/D multiplexed modeT16Y16T14W15
GPMC0_AD2IOGPMC Data 2 Input/Output in A/D non-multiplexed mode and additionally Address 3 Output in A/D multiplexed modeP15W17T15W16
GPMC0_AD3IOGPMC Data 3 Input/Output in A/D non-multiplexed mode and additionally Address 4 Output in A/D multiplexed modeF1G1D1D1
GPMC0_AD4IOGPMC Data 4 Input/Output in A/D non-multiplexed mode and additionally Address 5 Output in A/D multiplexed modeF4G2D2D2
GPMC0_AD5IOGPMC Data 5 Input/Output in A/D non-multiplexed mode and additionally Address 6 Output in A/D multiplexed modeG2E1D3C1
GPMC0_AD6IOGPMC Data 6 Input/Output in A/D non-multiplexed mode and additionally Address 7 Output in A/D multiplexed modeA9A11C10A11
GPMC0_AD7IOGPMC Data 7 Input/Output in A/D non-multiplexed mode and additionally Address 8 Output in A/D multiplexed modeD11D15B13B14
GPMC0_AD8IOGPMC Data 8 Input/Output in A/D non-multiplexed mode and additionally Address 9 Output in A/D multiplexed modeB9, E1B11, F2D8, E3B10, E3
GPMC0_AD9IOGPMC Data 9 Input/Output in A/D non-multiplexed mode and additionally Address 10 Output in A/D multiplexed modeR16Y17R15V16
GPMC0_AD10IOGPMC Data 10 Input/Output in A/D non-multiplexed mode and additionally Address 11 Output in A/D multiplexed modeD14C16A15
GPMC0_AD11OGPMC Data 11 Input/Output in A/D non-multiplexed mode and additionally Address 12 Output in A/D multiplexed modeN1R2M2N2
GPMC0_AD12OGPMC Data 12 Input/Output in A/D non-multiplexed mode and additionally Address 13 Output in A/D multiplexed modeN4R1N1N1
GPMC0_AD13IOGPMC Data 13 Input/Output in A/D non-multiplexed mode and additionally Address 14 Output in A/D multiplexed modeD13B17C14
GPMC0_AD14IOGPMC Data 14 Input/Output in A/D non-multiplexed mode and additionally Address 15 Output in A/D multiplexed modeA15B18B15
GPMC0_AD15IOGPMC Data 15 Input/Output in A/D non-multiplexed mode and additionally Address 16 Output in A/D multiplexed modeH2H1E1F1
GPMC0_BE0n_CLEOGPMC Lower-Byte Enable (active low) or Command Latch EnableC13A17A14A16
GPMC0_BE1nOGPMC Upper-Byte Enable (active low)B11C12A11B11
GPMC0_CSn0OGPMC Chip Select 0 (active low)A14, B8B10, B16B8, C13A10, A15
GPMC0_CSn1OGPMC Chip Select 1 (active low)G3H2E2E1
GPMC0_CSn2OGPMC Chip Select 2 (active low)U18Y19R16W18
GPMC0_CSn3OGPMC Chip Select 3 (active low)T18W19N14V18
GPMC0_WAIT0IGPMC External Indication of WaitC9D11B9
GPMC0_WAIT1IGPMC External Indication of WaitC7C7C8C9