AM2612

• Single and Dual Arm Cortex R5F CPU with each core running up to 500 MHz
  • 16KB I-Cache with 64-bit ECC per CPU core
  • 16KB D-cache with 32-bit ECC per CPU core
  • 256KB Tightly Coupled Memory (TCM) per core, with 32-bit ECC
  • Lockstep or Dual core operation supported
• Trigonometric Math Unit (TMU) for accelerating trigonometric functions
  • Up to 2 × TMU, one per R5F MCU core

• 1.5MB of On-Chip Shared SRAM (3 banks × 512KB). ECC error protection for full 1.5MB OCSRAM.

• 256KB Remote Low latency L2 cache (RL2), software programmable, shared between all cores, allocated from SRAM

• 1 × EDMA to support data movement functions
• Device Boot supported from the following interfaces:
  • UART (Primary/Backup)

  • OSPI NOR and NAND Flash (50MHz SDR and 25MHz DDR)

  • USB Peripheral boot
• Interprocessor communication modules
  • SPINLOCK module for synchronizing processes running on multiple R5F CPUs and HSM CPU
  • MAILBOX functionality implemented through CTRLMMR registers

• 2 × Octal Serial Peripheral Interface (OSPI) at up to 133-MHz SDR and 133-MHz DDR at 1.8V and 3.3V which can be used for
  • External flash memory with full XIP (eXecute In Place) support

  • RAM expansion/FOTA

• 1 × 4-bit Multi-Media Card/Secure Digital (MMC/SD) interface
• General-Purpose Memory Controller (GPMC)
  • 16-bit parallel data bus with 22-bit address bus and 4 chip selects
  • Up to 4MB addressable memory space
  • Integrated Error Location Module (ELM) support for error checking

General Connectivity:

• 6 × Universal Asynchronous RX-TX (UART) modules
• 4 × Serial Peripheral Interface (SPI) controllers
• 3 × Local Interconnect Network (LIN) ports
• 3 × Inter-Integrated Circuit (I2C) ports
• 2 × Modular Controller Area Network (MCAN) modules with CAN-FD support
• 1 × Fast Serial Interface Transmitter (FSITX) at up to 200Mbps
• 1 × Fast Serial Interface Receiver (FSIRX) at up to 200Mbps
• Up to 140 × General Purpose I/O (GPIO)

• Port configurable as USB host, USB device, or USB Dual-Role device
• USB 2.0 Host mode
  • High-Speed (HS, 480Mbps)
  • Full-Speed (FS, 12Mbps)
  • Low-Speed (LS, 1.5Mbps)
• USB 2.0 Device mode
  • High-Speed (HS, 480Mbps)
  • Full-Speed (FS, 12Mbps)

• Real-time Control Subsystem (CONTROLSS)
• Flexible Input/Output Crossbars (XBAR)
• 3 × 12-bit Analog to Digital Converters (ADC) with 3 MSPS maximum sampling rate
  • Each ADC module with
    • 7× Single ended channels OR
    • 3 × Differential channels
  • Highly configurable ADC digital logic
    • With selectable internal or external reference
    • 4 × Post-Processing blocks for each ADC module
• 9 × Analog Comparators with internal 12-bit DAC reference (CMPSS-A)
• 1 × 12 bit Digital to Analog Converter (DAC)
• 10 × Enhanced High Resolution Pulse Width Modulation (eHRPWM) modules
  • Single or Dual PWM channels
  • Advanced PWM Configurations
  • Enhanced HRPWM extends the time resolution of the PWM compared to EPWM
• 8 × Enhanced Capture (ECAP) modules
• 2 × Enhanced Quadrature Encoder Pulse (EQEP) modules
• 2 × Sigma-Delta Filter Modules (SDFM)

Industrial Connectivity:

• 2× Programmable Real-time Unit – Industrial Communication SubSystem(2× PRU-ICSS)
  • 2× PRU per ICSS for a total of 4 PRU cores
  • Dual core Programmable Realtime Unit Subsystem (PRU0 / PRU1)
    • Deterministic hardware
    • Dynamic firmware
  • 20-channel enhanced input (eGPI) per PRU
  • 20-channel enhanced output (eGPO) per PRU
  • Embedded Peripherals and Memory
    • 1 × UART, 1x ECAP
    • 1 × MDIO, 1x IEP
    • 1 × 32KB Shared General Purpose RAM
    • 2 × 8KB Shared Data RAM
    • 1 × 12KB IRAM per PRU
    • ScratchPad (SPAD), MAC/CRC
  • Digital encoder and sigma-delta control loops
  • The PRU-ICSS enables advanced industrial protocols including:
    • EtherCAT, Ethernet/IP™
    • PROFINET, IO-Link
  • Dedicated Interrupt Controller (INTC)
  • Dynamic CONTROLSS XBAR Integration
  • Supports standard ethernet (EMAC) – up to 2 external ports

• Integrated Ethernet Switch(CPSW3G)
  • Supporting two external ports and one internal port with selectable MII/ RMII/ RGMII
  • IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
  • Clause 45 MDIO PHY management
  • 512 × ALE engine based packet classifiers
  • Priority flow control with up to 2KB packet size
  • Four CPU hardware interrupt pacing
  • IP/ UDP/ TCP checksum offload in hardware
  • Supports TSN

• Hardware Security Module (HSM) with support for Auto SHE 1.1/EVITA
• Targeted for ISO 21434 compliance
• Secure boot support
  • Device Take Over Protection
  • Hardware enforced root-of-trust
  • Authenticated boot
  • SW Anti-rollback protection
• Debug security
  • Secure device debug only after proper authentication
  • Ability to disable device debug functionality
• Device ID and Key Management
  • Support for OTP Memory (FUSEROM)
    • Store root keys and other security fields
  • Separate EFUSE controllers and FUSE ROMs
  • Unique Device Public Identifiers
• Memory Protection Units (MPU)
  • Dedicated Arm MPU per Cortex-R5F core
  • System MPU - present at various interfaces in the SoC (MPU or Firewall)
  • 8 to 16 Programmable Regions
    • Enable/Privilege ID
    • Start/End Address
    • Read/Write/Cachable
    • Secure/Non-Secure
• Cryptographic acceleration
  • Cryptographic cores with DMA Support
  • AES - 128/192/256-bit key sizes
  • SHA2 - 256/384/512-bit support
  • DRBG with pseudo and true random number generator

• Enables design of systems with functional safety requirements
  • Error Signaling Module (ESM)
  • ECC or parity on calculation critical memories
  • Built-In Self-Test (BIST) on-chip RAM
  • Runtime internal diagnostic modules including voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engines for memory integrity checks
• Functional Safety-Compliant targeted [Industrial]
  • Developed for functional safety applications
  • Documentation to be made available to aid IEC 61508 functional safety system design
  • Systematic capability up to SIL-3 targeted
  • Hardware integrity up to SIL-3 targeted
  • Safety-related certification
    • IEC 61508 planned
• Functional Safety-Compliant targeted [Automotive]
  • Developed for functional safety applications
  • Documentation to be made available to aid ISO 26262 functional safety system design
  • Systematic capability up to ASIL-D targeted
  • Hardware integrity up to ASIL-D targeted
  • Safety-related certification
    • ISO 26262 planned

• AEC-Q100 qualified for automotive applications
• Package options
  • Available multiple NFBGA packages (see Section 3)
  • With 0.5mm, 0.65 mm and 0.8 mm pitch options