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AM2634

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Quad-core Arm® Cortex®-R5F MCU up to 400 MHz with real-time control and security

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AM2634

ACTIVE
Data sheet Order now

Product details

Frequency (MHz) 400 RAM (kByte) 2048 ADC type 12-bit SAR Number of GPIOs 140 UART 6 Features EtherCAT, EtherNet/IP, External memory interface, Hardware encrpytion (AES/DES/SHA/MD5), Integrated industrial protocols, Profinet TI functional safety category Functional Safety-Compliant Operating temperature range (°C) -40 to 105 Ethernet MAC only PWM (Ch) 64 SPI 5 CAN (#) 4 (CAN-FD) Communication interface ADC, CAN, CAN-FD, Ethernet, GPIO, I2C, QSPI, SD/SDIO, SPI, UART, eCAP, ePWM, eQEP
Frequency (MHz) 400 RAM (kByte) 2048 ADC type 12-bit SAR Number of GPIOs 140 UART 6 Features EtherCAT, EtherNet/IP, External memory interface, Hardware encrpytion (AES/DES/SHA/MD5), Integrated industrial protocols, Profinet TI functional safety category Functional Safety-Compliant Operating temperature range (°C) -40 to 105 Ethernet MAC only PWM (Ch) 64 SPI 5 CAN (#) 4 (CAN-FD) Communication interface ADC, CAN, CAN-FD, Ethernet, GPIO, I2C, QSPI, SD/SDIO, SPI, UART, eCAP, ePWM, eQEP
NFBGA (ZCZ) 324 225 mm² 15 x 15

Processor Cores:

  • Single, dual, and quad-core Arm Cortex-R5F MCU with each core running up to 400 MHz
    • 16KB I-cache with 64-bit ECC per CPU core
    • 16KB D-cache with 32-bit ECC per CPU core
    • 64KB Tightly-Coupled Memory (TCM) with 32-bit ECC per CPU core
    • Lockstep or Dual-core capable clusters

Memory Subsystem:

  • 2MB of On-Chip RAM (OCSRAM)
    • 4 Banks x 512KB
    • ECC error protection
    • Internal DMA engine support

System on Chip (SoC) Services and Architecture:

  • 1x EDMA to support data movement functions
  • Device Boot supported from the following interfaces:
    • UART (Primary/Backup)
    • QSPI NOR Flash (4S/1S) (Primary)
  • Interprocessor communication modules
    • SPINLOCK module for synchronizing processes running on multiple cores
    • MAILBOX functionality implemented through CTRLMMR registers
  • Central Platform Time Sync (CPTS) support with time-sync and compare-event interrupt routers

Media and Data Storage:

  • 1x 4-bit Multi-Media Card/Secure Digital (MMC/SD) interface
  • General-Purpose Memory Controller (GPMC)
    • 16-bit parallel data bus with 22-bit address bus
    • Up to 4MB addressable memory space
    • Integrated Error Location Module (ELM) support for error checking

General Connectivity:

  • 6x Universal Asynchronous RX-TX (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 5x Local Interconnect Network (LIN) ports
  • 4x Inter-Integrated Circuit (I2C) ports
  • 4x Modular Controller Area Network (MCAN) modules with CAN-FD support
  • 1x Quad Serial Peripheral Interface (QSPI)
  • 4x Fast Serial Interface Transmitters (FSITX)
  • 4x Fast Serial Interface Receivers (FSIRX)
  • Up to 139 General-Purpose I/O (GPIO) pins

Sensing & Actuation:

  • Real-time Control Subsystem (CONTROLSS)
  • Flexible Input/Output Crossbars (XBAR)
  • 5x 12-bit Analog-to-Digital Converters (ADC)
    • 6-input SAR ADC up to 4 MSPS
      • 6x Single-ended channels OR
      • 3x Differential channels
    • Highly Configurable ADC Digital Logic
      • XBAR Start of Conversion Triggers (SOC)
      • User-defined Sample and Hold (S+H)
      • Flexible Post-Processing Blocks (PPB)
  • 10x Analog Comparators with Type-A programmable DAC reference (CMPSSA)
  • 10x Analog Comparators with Type-B programmable DAC reference (CMPSSB)
  • 1x 12-bit Digital-to-Analog Converter (DAC)
  • 32x Pulse Width Modulation (EPWM) modules
    • Single or Dual PWM channels
    • Advanced PWM Configurations
    • Extended HRPWM time resolution
  • 10x Enhanced Capture (ECAP) modules
  • 3x Enhanced Quadrature Encoder Pulse (EQEP) modules
  • 2x 4-Ch Sigma-Delta Filter Modules (SDFM)
  • Additional Signal-multiplex Crossbars (XBAR)

Industrial Connectivity:

  • Programmable Real-Time Unit (PRU-SS) and PRU-Industrial Communication Subsystem (PRU-ICSS)
    • Dual core Programmable Realtime Unit Subsystem (PRU0 / PRU1)
      • Deterministic Hardware
      • Dynamic Firmware
    • 20-channel enhanced input (eGPI) per PRU
    • 20-channel enhanced output (eGPO) per PRU
    • Embedded Peripherals and Memory
      • 1x UART, 1x ECAP
      • 1x MDIO, 1x IEP,
      • 1x 32KB Shared General Purpose RAM
      • 2x 8KB Shared Data RAM
      • 1x 16KB IRAM per PRU
      • ScratchPad (SPAD), MAC/CRC
    • Digital encoder and sigma-delta control loops
    • The PRU-ICSS enables advanced industrial protocols including:
      • EtherCAT, Ethernet/IP™,
      • PROFINET, IO-Link for order
    • Dedicated Interrupt Controller (INTC)
    • Dynamic CONTROLSS XBAR Integration

High-Speed Interfaces:

  • Integrated Ethernet switch supporting two external ports
    • RMII (10/100) or RGMII (10/100/1000)
    • IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Clause 45 MDIO PHY management
    • 512x ALE engine-based Packet Classifiers
    • Priority flow control with up to 2KB packet size
    • Four CPU hardware interrupt pacing
    • IP/UDP/TCP checksum offload in hardware

Security:

  • Hardware Security Module (HSM) with support for Auto SHE 1.1/EVITA
  • Secure boot support
    • Device Take Over Protection
    • Hardware-enforced root-of-trust
    • Authenticated boot
    • SW Anti-rollback protection
  • Debug security
    • Secure device debug only after proper authentication
    • Ability to disable device debug functionality
  • Device ID and Key Management
    • Support for OTP Memory (FUSEROM)
      • Store root keys & other security fields
    • Separate EFUSE controllers and FUSE ROMs
    • Unique Public Device Identifiers (UIDs)
  • Memory Protection Units (MPU)
    • Dedicated Arm® MPU per Cortex®-R5F core
    • System MPU - present at various interfaces in the SoC (MPU or Firewall)
    • 8-16 Programmable Regions
      • Enable/Privilege ID
      • Start/End Address
      • Read/Write/Cachable
      • Secure/Non-Secure
  • Cryptographic Acceleration
    • Cryptographic cores with DMA Support
    • AES - 128/192/256-bit key sizes
    • SHA2 - 256/384/512-bit support
    • DRBG with pseudo and true random number generator
    • PKA (public key accelerator) to assist in RSA/ECC processing

Functional Safety:

  • Enables design of systems with functional safety requirements
    • Error Signaling Module (ESM) with designated SAFETY_ERRORn pin
    • ECC or parity on calculation-critical memories
    • Built-In Self-Test (BIST) and fault-injection for CPU and on-chip RAM
    • Runtime internal diagnostic modules including voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engines for memory integrity checks
  • Functional Safety-Compliant [Industrial]
    • Developed for functional safety applications
    • Documentation to be made available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL-3
    • Hardware integrity up to SIL-3
    • Safety-related certification
  • Functional Safety-Compliant [Automotive]
    • Developed for functional safety applications
    • Documentation to be made available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL-D
    • Hardware integrity up to ASIL-D
    • Safety-related certification

Technology / Package:

  • AEC-Q100 qualified for automotive applications
  • 45-nm technology
  • ZCZ Package
    • 324-pin NFBGA
    • 15.0 mm x 15.0 mm
    • 0.8 mm pitch

Processor Cores:

  • Single, dual, and quad-core Arm Cortex-R5F MCU with each core running up to 400 MHz
    • 16KB I-cache with 64-bit ECC per CPU core
    • 16KB D-cache with 32-bit ECC per CPU core
    • 64KB Tightly-Coupled Memory (TCM) with 32-bit ECC per CPU core
    • Lockstep or Dual-core capable clusters

Memory Subsystem:

  • 2MB of On-Chip RAM (OCSRAM)
    • 4 Banks x 512KB
    • ECC error protection
    • Internal DMA engine support

System on Chip (SoC) Services and Architecture:

  • 1x EDMA to support data movement functions
  • Device Boot supported from the following interfaces:
    • UART (Primary/Backup)
    • QSPI NOR Flash (4S/1S) (Primary)
  • Interprocessor communication modules
    • SPINLOCK module for synchronizing processes running on multiple cores
    • MAILBOX functionality implemented through CTRLMMR registers
  • Central Platform Time Sync (CPTS) support with time-sync and compare-event interrupt routers

Media and Data Storage:

  • 1x 4-bit Multi-Media Card/Secure Digital (MMC/SD) interface
  • General-Purpose Memory Controller (GPMC)
    • 16-bit parallel data bus with 22-bit address bus
    • Up to 4MB addressable memory space
    • Integrated Error Location Module (ELM) support for error checking

General Connectivity:

  • 6x Universal Asynchronous RX-TX (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 5x Local Interconnect Network (LIN) ports
  • 4x Inter-Integrated Circuit (I2C) ports
  • 4x Modular Controller Area Network (MCAN) modules with CAN-FD support
  • 1x Quad Serial Peripheral Interface (QSPI)
  • 4x Fast Serial Interface Transmitters (FSITX)
  • 4x Fast Serial Interface Receivers (FSIRX)
  • Up to 139 General-Purpose I/O (GPIO) pins

Sensing & Actuation:

  • Real-time Control Subsystem (CONTROLSS)
  • Flexible Input/Output Crossbars (XBAR)
  • 5x 12-bit Analog-to-Digital Converters (ADC)
    • 6-input SAR ADC up to 4 MSPS
      • 6x Single-ended channels OR
      • 3x Differential channels
    • Highly Configurable ADC Digital Logic
      • XBAR Start of Conversion Triggers (SOC)
      • User-defined Sample and Hold (S+H)
      • Flexible Post-Processing Blocks (PPB)
  • 10x Analog Comparators with Type-A programmable DAC reference (CMPSSA)
  • 10x Analog Comparators with Type-B programmable DAC reference (CMPSSB)
  • 1x 12-bit Digital-to-Analog Converter (DAC)
  • 32x Pulse Width Modulation (EPWM) modules
    • Single or Dual PWM channels
    • Advanced PWM Configurations
    • Extended HRPWM time resolution
  • 10x Enhanced Capture (ECAP) modules
  • 3x Enhanced Quadrature Encoder Pulse (EQEP) modules
  • 2x 4-Ch Sigma-Delta Filter Modules (SDFM)
  • Additional Signal-multiplex Crossbars (XBAR)

Industrial Connectivity:

  • Programmable Real-Time Unit (PRU-SS) and PRU-Industrial Communication Subsystem (PRU-ICSS)
    • Dual core Programmable Realtime Unit Subsystem (PRU0 / PRU1)
      • Deterministic Hardware
      • Dynamic Firmware
    • 20-channel enhanced input (eGPI) per PRU
    • 20-channel enhanced output (eGPO) per PRU
    • Embedded Peripherals and Memory
      • 1x UART, 1x ECAP
      • 1x MDIO, 1x IEP,
      • 1x 32KB Shared General Purpose RAM
      • 2x 8KB Shared Data RAM
      • 1x 16KB IRAM per PRU
      • ScratchPad (SPAD), MAC/CRC
    • Digital encoder and sigma-delta control loops
    • The PRU-ICSS enables advanced industrial protocols including:
      • EtherCAT, Ethernet/IP™,
      • PROFINET, IO-Link for order
    • Dedicated Interrupt Controller (INTC)
    • Dynamic CONTROLSS XBAR Integration

High-Speed Interfaces:

  • Integrated Ethernet switch supporting two external ports
    • RMII (10/100) or RGMII (10/100/1000)
    • IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Clause 45 MDIO PHY management
    • 512x ALE engine-based Packet Classifiers
    • Priority flow control with up to 2KB packet size
    • Four CPU hardware interrupt pacing
    • IP/UDP/TCP checksum offload in hardware

Security:

  • Hardware Security Module (HSM) with support for Auto SHE 1.1/EVITA
  • Secure boot support
    • Device Take Over Protection
    • Hardware-enforced root-of-trust
    • Authenticated boot
    • SW Anti-rollback protection
  • Debug security
    • Secure device debug only after proper authentication
    • Ability to disable device debug functionality
  • Device ID and Key Management
    • Support for OTP Memory (FUSEROM)
      • Store root keys & other security fields
    • Separate EFUSE controllers and FUSE ROMs
    • Unique Public Device Identifiers (UIDs)
  • Memory Protection Units (MPU)
    • Dedicated Arm® MPU per Cortex®-R5F core
    • System MPU - present at various interfaces in the SoC (MPU or Firewall)
    • 8-16 Programmable Regions
      • Enable/Privilege ID
      • Start/End Address
      • Read/Write/Cachable
      • Secure/Non-Secure
  • Cryptographic Acceleration
    • Cryptographic cores with DMA Support
    • AES - 128/192/256-bit key sizes
    • SHA2 - 256/384/512-bit support
    • DRBG with pseudo and true random number generator
    • PKA (public key accelerator) to assist in RSA/ECC processing

Functional Safety:

  • Enables design of systems with functional safety requirements
    • Error Signaling Module (ESM) with designated SAFETY_ERRORn pin
    • ECC or parity on calculation-critical memories
    • Built-In Self-Test (BIST) and fault-injection for CPU and on-chip RAM
    • Runtime internal diagnostic modules including voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engines for memory integrity checks
  • Functional Safety-Compliant [Industrial]
    • Developed for functional safety applications
    • Documentation to be made available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL-3
    • Hardware integrity up to SIL-3
    • Safety-related certification
  • Functional Safety-Compliant [Automotive]
    • Developed for functional safety applications
    • Documentation to be made available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL-D
    • Hardware integrity up to ASIL-D
    • Safety-related certification

Technology / Package:

  • AEC-Q100 qualified for automotive applications
  • 45-nm technology
  • ZCZ Package
    • 324-pin NFBGA
    • 15.0 mm x 15.0 mm
    • 0.8 mm pitch

The AM263x Sitara™ Arm® Microcontrollers are built to meet the complex real-time processing needs of next generation industrial and automotive embedded products. The AM263x MCU family consists of multiple pin-to-pin compatible devices with up to four 400 MHz Arm® Cortex®-R5F cores. As an option, the Arm® R5F subsystem can be programmed to run in lockstep or dual-core mode for a multiple functional safety configurations. The industrial communications subsystem (PRU-ICSS) enables integrated industrial Ethernet communication protocols such as PROFINET®, TSN, Ethernet/IP®, EtherCAT® (among many others), standard Ethernet connectivity, and even custom I/O interfaces. The family is designed for the future of motor control and digital power applications with advanced analog sensing and digital actuation modules.

The multiple R5F cores are arranged in cluster subsystems with 256KB of shared tightly coupled memory (TCM) along with 2MB of shared SRAM, greatly reducing the need for external memory. Extensive ECC is included for on-chip memories, peripherals, and interconnects for enhanced reliability. Granular firewalls managed by the Hardware Security Manager (HSM) enable developers to implement stringent security-minded system design requirements. Cryptographic acceleration and secure boot are also available on AM263x devices.

TI provides a complete set of microcontroller software and development tools for the AM263x family of microcontrollers.

The AM263x Sitara™ Arm® Microcontrollers are built to meet the complex real-time processing needs of next generation industrial and automotive embedded products. The AM263x MCU family consists of multiple pin-to-pin compatible devices with up to four 400 MHz Arm® Cortex®-R5F cores. As an option, the Arm® R5F subsystem can be programmed to run in lockstep or dual-core mode for a multiple functional safety configurations. The industrial communications subsystem (PRU-ICSS) enables integrated industrial Ethernet communication protocols such as PROFINET®, TSN, Ethernet/IP®, EtherCAT® (among many others), standard Ethernet connectivity, and even custom I/O interfaces. The family is designed for the future of motor control and digital power applications with advanced analog sensing and digital actuation modules.

The multiple R5F cores are arranged in cluster subsystems with 256KB of shared tightly coupled memory (TCM) along with 2MB of shared SRAM, greatly reducing the need for external memory. Extensive ECC is included for on-chip memories, peripherals, and interconnects for enhanced reliability. Granular firewalls managed by the Hardware Security Manager (HSM) enable developers to implement stringent security-minded system design requirements. Cryptographic acceleration and secure boot are also available on AM263x devices.

TI provides a complete set of microcontroller software and development tools for the AM263x family of microcontrollers.

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AM2631 ACTIVE Single-core Arm® Cortex®-R5F MCU up to 400 MHz with real-time control and security Same device with single core support
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AM2632 ACTIVE Dual-core Arm® Cortex®-R5F MCU up to 400 MHz with real-time control and security Same device with dual core support
AM2632-Q1 ACTIVE Automotive dual-core Arm® Cortex®-R5F MCU up to 400 MHz with real-time control and security Same device with dual core support and auto quality Q100 for your automotive needs
AM2634-Q1 ACTIVE Automotive quad-core Arm® Cortex®-R5F MCU up to 400 MHz with real-time control and security Same device with auto quality Q100 for your automotive needs

Technical documentation

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Type Title Date
* Data sheet AM263x Sitara™ Microcontrollers datasheet (Rev. D) PDF | HTML 27 Jul 2023
* Errata AM263x Sitara™ Microcontroller Silicon Revision 1.0A, 1.1A (Rev. E) PDF | HTML 24 May 2024
* User guide AM263x Sitara Processors Technical Reference Manual Register Addendum (Rev. D) 08 Dec 2023
User guide AM263x Sitara™ Microcontroller Technical Reference Manual (Rev. F) 20 Mar 2024
Application note AM263x Control Card Quick Start Guide PDF | HTML 12 Jan 2024
Application note Clock Edge Delay Compensation With Isolated Modulators Digital Interface to MCUs (Rev. A) PDF | HTML 12 Jan 2024
Product overview Functional Safety for AM2x and Hercules™ Microcontrollers PDF | HTML 08 Nov 2023
Application note AM263 to AM263P Migration Overview PDF | HTML 03 Nov 2023
Application note AM263x and AM263Px Hardware Design Guidelines (Rev. B) PDF | HTML 03 Nov 2023
White paper 실시간 제어 처리 가속화: 검증된MCU부터 차세대 MCU까지 PDF | HTML 24 Oct 2023
White paper Accelerated Real-Time Control Processing: From Tried-and-True to Next-Gen. MCUs PDF | HTML 06 Oct 2023
User guide AM263x Sitara Control Card Hardware User's Guide (Rev. D) PDF | HTML 14 Sep 2023
Application note Sitara MCU Thermal Design PDF | HTML 11 Sep 2023
Functional safety information AM263x Software Diagnostics Library TUV SUD Functional Safety Certificate 23 Aug 2023
Application note Using the Sitara MCU AM263x in an Automotive SiC Traction Inverter PDF | HTML 16 Aug 2023
Application note Integration of MbedTLS on SITARA MCU Devices PDF | HTML 03 Aug 2023
Functional safety information AM263x IEC 61508 Certificate Report 31 Jul 2023
Functional safety information AM263x ISO26262 Certificate Report 31 Jul 2023
Functional safety information AM263x IEC61508 TUV SUD Safety Certificate 26 Jul 2023
User guide 10-kW, Three-Phase, Three-Level (T-Type) Inverter Using AM263 PDF | HTML 11 Jul 2023
Application note AM263x Device Nomenclature and Subset Devices PDF | HTML 03 Jul 2023
Certificate BP-AM2BLDCSERVO EU Declaration of Conformity (DoC) 28 Jun 2023
Application note Intra Drive Communication Using 8b-10b Line Code With Programmable Real Time Uni PDF | HTML 24 May 2023
Application note AM263x QSPI Flash Selection Guide (Rev. A) PDF | HTML 23 Mar 2023
Application note Monitoring Bus Voltage and Power Measurement on AM263x MCU Using INA226 PDF | HTML 02 Mar 2023
Application note Interfacing 5V Sensors and Signals to 3.3V Input SAR ADCs PDF | HTML 09 Feb 2023
White paper Design Priorities in EV Traction Inverter With Optimum Performance (Rev. A) PDF | HTML 08 Feb 2023
Application note DCC Computation Tool PDF | HTML 03 Feb 2023
Application note Debugging Sitara AM2x Microcontrollers PDF | HTML 24 Oct 2022
Application note AM263x Power Estimation Tool PDF | HTML 20 Oct 2022
Application note AM263x SW Build Sheet 17 Oct 2022
Application note PRU-ICSS Feature Comparison (Rev. G) PDF | HTML 11 Oct 2022
White paper 具備最佳性能的 EV 牽引逆變器設計優先順序 PDF | HTML 27 Sep 2022
White paper 최적의성능을 갖춘 EV 트랙션 인버터에서 설계 우선 순위 PDF | HTML 27 Sep 2022
White paper Traction Inverters – A Driving Force Behind Vehicle Electrification PDF | HTML 08 Sep 2022
White paper 牽引逆變器 – 車輛電氣化背後的驅動力量 PDF | HTML 17 Aug 2022
White paper 트랙션 인버터 – 차량 전기화를 이끄는 동력 PDF | HTML 17 Aug 2022
Application note Optimized Trigonometric Functions on TI Arm Cores (Rev. A) PDF | HTML 08 Aug 2022
Application note AM263x Benchmarks PDF | HTML 09 May 2022
Technical article What is “real-time control” and why do you need it? PDF | HTML 06 Apr 2022
Application note AM263x for Traction Inverters PDF | HTML 21 Mar 2022
Technical article How MCUs can unlock the full potential of electrification designs PDF | HTML 21 Mar 2022
Functional safety information The state of functional safety in Industry 4.0 27 Nov 2018
White paper Time Sensitive Networking for Industrial Automation (Rev. C) 31 Jul 0202

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