SWRS245B December   2021  – December 2023 AM2732 , AM2732-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
      1. 5.1.1 AM273x ZCE Pin Diagram
      2. 5.1.2 AM273x NZN Pin Diagram
    2. 5.2 Pin Attributes (AM273x ZCE, NZN Packages)
      1.      13
    3. 5.3 Signal Descriptions
      1. 5.3.1  ADC Signal Descriptions
        1.       16
      2. 5.3.2  CPTS Signal Descriptions
        1.       18
      3. 5.3.3  CSI 2.0 Signal Descriptions
        1.       20
      4. 5.3.4  DMM Signal Descriptions
        1.       22
      5. 5.3.5  ECAP Signal Descriptions
        1.       24
      6. 5.3.6  EPWM Signal Descriptions
        1.       26
        2.       27
        3.       28
        4.       29
      7. 5.3.7  GPIO Signal Descriptions
        1.       31
        2.       32
      8. 5.3.8  I2C Signal Descriptions
        1.       34
        2.       35
        3.       36
      9. 5.3.9  Clock Signal Descriptions
        1.       38
        2.       39
      10. 5.3.10 JTAG Signal Descriptions
        1.       41
      11. 5.3.11 LVDS Signal Descriptions
        1.       43
      12. 5.3.12 MCAN Signal Descriptions
        1.       45
        2.       46
      13. 5.3.13 MCASP Signal Descriptions
        1.       48
        2.       49
        3.       50
      14. 5.3.14 Ethernet Signal Descriptions
        1.       52
        2.       53
        3.       54
        4.       55
      15. 5.3.15 GPIO Signal Descriptions
        1.       57
        2.       58
      16. 5.3.16 Power Supply Signal Descriptions
        1.       60
      17. 5.3.17 QSPI Signal Descriptions
        1.       62
      18. 5.3.18 Reserverd Signal Descriptions
        1.       64
      19. 5.3.19 UART Signal Descriptions
        1.       66
        2.       67
      20. 5.3.20 SPI Signal Descriptions
        1.       69
        2.       70
        3.       71
        4.       72
      21. 5.3.21 System Signal Descriptions
        1.       74
      22. 5.3.22 Trace Signal Descriptions
        1.       76
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings - Automotive
    3. 6.3  Power-On Hours (POH)
      1. 6.3.1 Automotive Temperature Profile
      2. 6.3.2 Industrial Temperature Profile
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Operating Performance Points
    6. 6.6  Power Supply Specifications
    7. 6.7  I/O Buffer Type and Voltage Rail Dependency
    8. 6.8  CPU Specifications
    9. 6.9  Thermal Resistance Characteristics for nFBGA Package [ZCE285A]
    10. 6.10 Thermal Resistance Characteristics for nFBGA Package [NZN225A]
    11. 6.11 Power Consumption Summary
    12. 6.12 Timing and Switching Characteristics
      1. 6.12.1 Power Supply Sequencing and Reset Timing
      2. 6.12.2 Clock Specifications
      3. 6.12.3 Peripheral Information
        1. 6.12.3.1  QSPI Flash Memory Peripheral
          1. 6.12.3.1.1 QSPI Timing Conditions
          2. 6.12.3.1.2 QSPI Timing Requirements
          3. 6.12.3.1.3 QSPI Switching Characteristics
        2. 6.12.3.2  MIBSPI Peripheral
          1. 6.12.3.2.1 SPI Timing Conditions
          2. 6.12.3.2.2 SPI Master Mode Timing and Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. 6.12.3.2.3 SPI Master Mode Timing and Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          4. 6.12.3.2.4 SPI Slave Mode Timing and Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        3. 6.12.3.3  Ethernet Switch (RGMII/RMII/MII) Peripheral
          1. 6.12.3.3.1  RGMII/GMII/MII Timing Conditions
          2. 6.12.3.3.2  RGMII Transmit Clock Switching Characteristics
          3. 6.12.3.3.3  RGMII Transmit Data and Control Switching Characteristics
          4. 6.12.3.3.4  RGMII Recieve Clock Timing Requirements
          5. 6.12.3.3.5  RGMII Recieve Data and Control Timing Requirements
          6. 6.12.3.3.6  RMII Transmit Clock Switching Characteristics
          7. 6.12.3.3.7  RMII Transmit Data and Control Switching Characteristics
          8. 6.12.3.3.8  RMII Receive Clock Timing Requirements
          9. 6.12.3.3.9  RMII Receive Data and Control Timing Requirements
          10. 6.12.3.3.10 MII Transmit Switching Characteristics
          11. 6.12.3.3.11 MII Receive Clock Timing Requirements
          12. 6.12.3.3.12 MII Receive Timing Requirements
          13. 6.12.3.3.13 MII Transmit Clock Timing Requirements
          14. 6.12.3.3.14 MDIO Interface Timings
        4. 6.12.3.4  LVDS/Aurora Instrumentation and Measurement Peripheral
          1. 6.12.3.4.1 LVDS Interface Configuration
          2. 6.12.3.4.2 LVDS Interface Timings
        5. 6.12.3.5  UART Peripheral
          1. 6.12.3.5.1 UART Timing Requirements
        6. 6.12.3.6  I2C Protocol Definition
          1. 6.12.3.6.1 I2C Timing Requirements #GUID-D615B3D8-5F52-430D-93CB-70204118ACE4/T4362547-185
        7. 6.12.3.7  Controller Area Network - Flexible Data-Rate (CAN-FD)
          1. 6.12.3.7.1 Dynamic Characteristics for the CAN-FD TX and RX Pins
        8. 6.12.3.8  CSI-2 Peripheral
        9. 6.12.3.9  General Purpose ADC (GPADC)
        10. 6.12.3.10 Enhanced Pulse-Width Modulator (ePWM)
        11. 6.12.3.11 Enhanced Capture (eCAP)
        12. 6.12.3.12 General-Purpose Input/Output
          1. 6.12.3.12.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) #GUID-1BEBEADE-CEC6-42DA-A124-5081550EEDD7/T4362547-45 #GUID-1BEBEADE-CEC6-42DA-A124-5081550EEDD7/T4362547-50
      4. 6.12.4 Emulation and Debug
        1. 6.12.4.1 Emulation and Debug Description
        2. 6.12.4.2 JTAG Interface
          1. 6.12.4.2.1 Timing Requirements for IEEE 1149.1 JTAG
          2. 6.12.4.2.2 Switching Characteristics for IEEE 1149.1 JTAG
        3. 6.12.4.3 ETM Trace Interface
          1. 6.12.4.3.1 ETM TRACE Timing Requirements
          2. 6.12.4.3.2 ETM TRACE Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Main Subsystem
    3. 7.3 DSP Subsystem
    4. 7.4 Radar Control Subsystem
    5. 7.5 Other Subsystems
      1. 7.5.1 Radar A2D Data Format Over CSI2 Interface
      2. 7.5.2 ADC Channels (Service) for User Application
    6. 7.6 Boot Modes
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Typical Application
      1. 8.1.1 Schematic
      2. 8.1.2 Layout
        1. 8.1.2.1 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • NZN|225
  • ZCE|285
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Table 5-29 MSS GPIO Signal Descriptions
Signal NameSignal TypeDescriptionZCE PINNZN PIN
MSS_GPIO_0IOMaster sub-system GPIOH1, V9B10, F3, P4
MSS_GPIO_1IOMaster sub-system GPIOJ1, J2A10, F2, G1
MSS_GPIO_2IOMaster sub-system GPIOH2, K2, U18A9, F1, G2, N13
MSS_GPIO_3IOMaster sub-system GPIOB2, H18, W18B3, C9, F15, P12
MSS_GPIO_4IOMaster sub-system GPIOD19, G17B15, B9, E13
MSS_GPIO_5IOMaster sub-system GPIOD18, G19B14, E14
MSS_GPIO_6IOMaster sub-system GPIOF19, F2C1, D15
MSS_GPIO_7IOMaster sub-system GPIOE1, G18D1, E15
MSS_GPIO_8IOMaster sub-system GPIOB3, C2, U18B2, B4, N13
MSS_GPIO_9IOMaster sub-system GPIOB19, D2, W18A13, A2, A8, P12
MSS_GPIO_10IOMaster sub-system GPIOB18, D1A12, B8, C2
MSS_GPIO_11IOMaster sub-system GPIOC17, E2A7, B1, C12
MSS_GPIO_12IOMaster sub-system GPIOA18, E18B12, C15
MSS_GPIO_13IOMaster sub-system GPIOB17, H1A11, F3
MSS_GPIO_14IOMaster sub-system GPIOA17, G1B11, E3
MSS_GPIO_15IOMaster sub-system GPIOB16, G2C11, E1
MSS_GPIO_16IOMaster sub-system GPIOC15, J2B7, F2
MSS_GPIO_17IOMaster sub-system GPIOA16, C3C7, D4
MSS_GPIO_18IOMaster sub-system GPIOB15, D4B6, C4
MSS_GPIO_19IOMaster sub-system GPIOA15, C1A3, A6
MSS_GPIO_20IOMaster sub-system GPIOB1, B14A4, B5
MSS_GPIO_21IOMaster sub-system GPIOC13, C18A5, B13
MSS_GPIO_22IOMaster sub-system GPIOC19A14, B10
MSS_GPIO_23IOMaster sub-system GPIOC5A10, C5
MSS_GPIO_24IOMaster sub-system GPIOD6A9, C6
MSS_GPIO_25IOMaster sub-system GPIOE3C9, D2
MSS_GPIO_26IOMaster sub-system GPIOH2B9, F1
MSS_GPIO_27IOMaster sub-system GPIOF1A8, D3
MSS_GPIO_28IOMaster sub-system GPIOG3B8, E2
MSS_GPIO_29IOMaster sub-system GPIOE17A7, C14
MSS_GPIO_30IOMaster sub-system GPIOA2, P19C3, M14
MSS_GPIO_31IOMaster sub-system GPIOR19, V16M15, P11