SPRSPB0 December   2024 AM2754-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
      1. 5.1.1 ANJ Pin Diagram
    2. 5.2 Pin Attributes
      1.      12
      2.      13
    3. 5.3 Signal Descriptions
      1.      15
      2. 5.3.1  ADC
        1.       17
      3. 5.3.2  Audio Clock References
        1.       19
      4. 5.3.3  CPSW
        1.       21
        2.       22
        3.       23
        4.       24
        5.       25
      5. 5.3.4  CPTS
        1.       27
      6. 5.3.5  ECAP
        1.       29
        2.       30
        3.       31
        4.       32
        5.       33
        6.       34
      7. 5.3.6  Emulation and Debug
        1.       36
        2.       37
      8. 5.3.7  EPWM
        1.       39
        2.       40
        3.       41
        4.       42
      9. 5.3.8  GPIO
        1.       44
        2.       45
        3.       46
      10. 5.3.9  HYPERBUS
        1.       48
      11. 5.3.10 I2C
        1.       50
        2.       51
        3.       52
        4.       53
        5.       54
        6.       55
        7.       56
        8.       57
      12. 5.3.11 MCAN
        1.       59
        2.       60
        3.       61
        4.       62
        5.       63
      13. 5.3.12 MCASP
        1.       65
        2.       66
        3.       67
        4.       68
        5.       69
      14. 5.3.13 MLB
        1.       71
      15. 5.3.14 MMC
        1.       73
      16. 5.3.15 OSPI
        1.       75
        2.       76
      17. 5.3.16 Power Supply
        1.       78
      18. 5.3.17 Reserved
        1.       80
      19. 5.3.18 System and Miscellaneous
        1.       82
        2.       83
        3.       84
        4.       85
      20. 5.3.19 SPI
        1.       87
        2.       88
        3.       89
        4.       90
        5.       91
      21. 5.3.20 TIMER
        1.       93
        2.       94
      22. 5.3.21 UART
        1.       96
        2.       97
        3.       98
        4.       99
        5.       100
        6.       101
        7.       102
        8.       103
      23. 5.3.22 USB
        1.       105
    4.     Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Electrostatic Discharge (ESD) for AEC - Q100 devices
    3. 6.3  Electrostatic Discharge (ESD) for non AEC - Q100 devices
    4. 6.4  Power-On Hours (POH) Summary
    5. 6.5  Automotive Temperature Profile
    6. 6.6  Recommended Operating Conditions
    7. 6.7  Operating Performance Points
    8. 6.8  Electrical Characteristics
      1. 6.8.1 I2C Open-Drain and Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.8.2 Fail-Safe Reset (FS RESET) Electrical Characteristics
      3. 6.8.3 High-Frequency Oscillators (MCU_OSC0 and OSC1) Electrical Characteristics
      4. 6.8.4 Low-Frequency Oscillator (WKUP_LFOSC0) Electrical Characteristics
      5. 6.8.5 SDIO Electrical Characteristics
      6. 6.8.6 Analog-to-Digital Converter (ADC)
      7. 6.8.7 LVCMOS Electrical Characteristics
      8. 6.8.8 USB2PHY Electrical Characteristics
    9. 6.9  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.9.1 VPP Specifications
      2. 6.9.2 Hardware Requirements
      3. 6.9.3 Programming Sequence
      4. 6.9.4 Impact to Your Hardware Warranty
    10. 6.10 Thermal Resistance Characteristics
      1. 6.10.1 Package Thermal Characteristics
    11. 6.11 Timing and Switching Characteristics
      1. 6.11.1 Timing Parameters and Information
      2. 6.11.2 Power Supply Requirements
        1. 6.11.2.1 Power Supply Slew Rate Requirement
        2. 6.11.2.2 Power Supply Sequencing
          1. 6.11.2.2.1 Power-Up Sequencing without IO Retention
          2. 6.11.2.2.2 Power-Up Sequencing with IO Retention
          3. 6.11.2.2.3 Power-Up Sequencing - IO Retention Wakeup
          4. 6.11.2.2.4 Power-Down Sequencing
      3. 6.11.3 System Timing
        1. 6.11.3.1 Reset Timing
          1.        Reset Timing Conditions
          2.        MCU_PORz Timing Requirements
          3.        144
          4.        RESETSTATz Switching Characteristics
          5.        MCU_RESETz Timing Requirements
          6.        RESETSTATz Switching Characteristics
          7.        EMUx Timing Requirements
          8.        149
          9.        BOOTMODE Timing Requirements
        2. 6.11.3.2 Error Signal Timing
          1.        Error Signal Timing Conditions
          2.        MCU_ERRORn Switching Characteristics
          3. 6.11.3.2.1 154
        3. 6.11.3.3 Clock Timing
          1.        Clock Timing Conditions
          2.        Clock Timing Requirements
          3. 6.11.3.3.1 158
          4.        Clock Switching Characteristics
          5. 6.11.3.3.2 160
      4. 6.11.4 Clock Specifications
        1. 6.11.4.1 Input Clocks / Oscillators
          1. 6.11.4.1.1 MCU_OSC0 and OSC1 Internal Oscillator Clock Source
            1. 6.11.4.1.1.1 HFOSC (MCU_OSC0 and OSC1) Crystal Circuit Requirements
            2. 6.11.4.1.1.2 HFOSC (MCU_OSC0 and OSC1) Switching Characteristics - Crystal Mode
            3. 6.11.4.1.1.3 Load Capacitance
            4. 6.11.4.1.1.4 Shunt Capacitance
          2. 6.11.4.1.2 MCU_OSC0 and OSC1 LVCMOS Digital Clock Source
          3. 6.11.4.1.3 WKUP_LFOSC0 Internal Oscillator Clock Source
            1. 6.11.4.1.3.1 LFOSC (WKUP_LFOSC0) Crystal Circuit Requirements
            2. 6.11.4.1.3.2 LFOSC (WKUP_LFOSC0) Switching Characteristics - Crystal Mode
          4. 6.11.4.1.4 WKUP_LFOSC0 LVCMOS Digital Clock Source
          5. 6.11.4.1.5 WKUP_LFOSC0 Not Used
        2. 6.11.4.2 Recommended System Precautions for Clock and Control Signal Transitions
      5. 6.11.5 Peripherals
        1. 6.11.5.1  ATL
          1.        ATL Timing Conditions
          2.        ATL_AWS[x] Timing Requirements
          3.        ATL_BWS[x] Timing Requirements
          4.        ATL_PCLK Timing Requirements
          5.        ATCLK[x] Switching Characteristics
        2. 6.11.5.2  CPSW3G
          1. 6.11.5.2.1 CPSW3G MDIO Timing
            1.         CPSW3G MDIO Timing Conditions
            2.         CPSW3G MDIO Timing Requirements
            3.         CPSW3G MDIO Switching Characteristics
            4.         187
          2. 6.11.5.2.2 CPSW3G RMII Timing
            1.         CPSW3G RMII Timing Conditions
            2.         CPSW3G RMII[x]_REFCLK Timing Requirements - RMII Mode
            3.         191
            4.         CPSW3G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER Timing Requirements - RMII Mode
            5.         193
            6.         CPSW3G RMII[x]_TXD[1:0], and RMII[x]_TXEN Switching Characteristics - RMII Mode
            7.         195
          3. 6.11.5.2.3 CPSW3G RGMII Timing
            1.         CPSW3G RGMII Timing Conditions
            2.         CPSW3G RGMII[x]_RCLK Timing Requirements - RGMII Mode
            3.         CPSW3G RGMII[x]_RD[3:0], and RGMII[x]_RCTL Timing Requirements - RGMII Mode
            4.         200
            5.         CPSW3G RGMII[x]_TCLK Switching Characteristics - RGMII Mode
            6.         CPSW3G RGMII[x]_TD[3:0], and RGMII[x]_TCTL Switching Characteristics - RGMII Mode
            7.         203
        3. 6.11.5.3  ECAP
          1.        ECAP Timing Conditions
          2.        ECAP Timing Requirements
          3.        207
          4.        ECAP Switching Characteristics
          5.        209
        4. 6.11.5.4  Emulation and Debug
          1. 6.11.5.4.1 Trace
            1.         Trace Timing Conditions
            2.         Trace Switching Characteristics
            3.         214
          2. 6.11.5.4.2 JTAG
            1.         JTAG Timing Conditions
            2.         JTAG Timing Requirements
            3.         JTAG Switching Characteristics
            4.         219
        5. 6.11.5.5  EPWM
          1.        EPWM Timing Conditions
          2.        EPWM Timing Requirements
          3.        223
          4.        EPWM Switching Characteristics
          5.        225
        6. 6.11.5.6  GPIO
          1.        GPIO Timing Conditions
          2.        GPIO Timing Requirements
          3.        GPIO Switching Characteristics
        7. 6.11.5.7  HyperBus
          1.        HyperBus Timing Conditions
          2.        HyperBus Timing Requirements
          3.        HyperBus 166MHz Switching Characteristics
          4.        HyperBus 100MHz Switching Characteristics
        8. 6.11.5.8  I2C
        9. 6.11.5.9  MCAN
          1.        MCAN Timing Conditions
          2.        MCAN Switching Characteristics
        10. 6.11.5.10 MCASP
          1.        MCASP Timing Conditions
          2.        MCASP Timing Requirements
          3.        242
          4.        MCASP Switching Characteristics
          5.        244
        11. 6.11.5.11 MCSPI
          1.        MCSPI Timing Conditions
          2.        MCSPI Timing Requirements - Controller Mode
          3.        248
          4.        MCSPI Switching Characteristics - Controller Mode
          5.        250
          6.        MCSPI Timing Requirements - Peripheral Mode
          7.        252
          8.        MCSPI Switching Characteristics - Peripheral Mode
          9.        254
        12. 6.11.5.12 MLB
          1.        MLB Timing Conditions
          2.        MLB Timing Requirements for MLBCLK - 3-pin
          3.        MLB Timing Requirements for Receive Data - 3-pin
          4.        MLB Switching Characteristics - 3-Pin
          5.        MLB Timing Requirements for MLBCLK - 6-pin
          6.        MLB Timing Requirements for Receive Data - 6-pin
          7.        MLB Switching Characteristics - 6-Pin
        13. 6.11.5.13 MMCSD
          1. 6.11.5.13.1 MMC0 - eMMC/SDIO Interface
            1.         MMC Timing Conditions
            2.         MMC Timing Requirements - 3.3V Legacy SDR Mode
            3.         267
            4.         MMC Switching Characteristics - 3.3V Legacy SDR Mode
            5.         269
            6.         MMC Timing Requirements - 3.3V High Speed SDR Mode
            7.         271
            8.         MMC Switching Characteristics - 3.3V High Speed SDR Mode
            9.         273
            10.         MMC Timing Requirements - 1.8V Legacy SDR, UHS-I SDR12 Mode
            11.         275
            12.         MMC Switching Characteristics - 1.8V Legacy SDR, UHS-I SDR12 Mode
            13.         277
            14.         MMC Timing Requirements - 1.8V High Speed SDR, UHS-I SDR25 Mode
            15.         279
            16.         MMC Switching Characteristics - 1.8V High Speed SDR, UHS-I SDR25 Mode
            17.         281
            18.         MMC Switching Characteristics - UHS-I SDR50 Mode
            19.         283
            20.         MMC Switching Characteristics - UHS-I DDR50 Mode
            21.         285
            22.         MMC Switching Characteristics - HS200 Mode
            23.         287
        14. 6.11.5.14 OSPI
          1.        OSPI Timing Conditions
          2. 6.11.5.14.1 OSPI0 PHY Mode
            1. 6.11.5.14.1.1 OSPI0 With PHY Data Training
              1.          OSPI DLL Delay Mapping for PHY Data Training
              2.          OSPI Timing Requirements - PHY Data Training
              3.          294
              4.          OSPI Switching Characteristics - PHY Data Training
              5.          296
            2. 6.11.5.14.1.2 OSPI0 Without Data Training
              1. 6.11.5.14.1.2.1 OSPI0 PHY SDR Timing
                1.           OSPI DLL Delay Mapping for PHY SDR Timing Modes
                2.           OSPI Timing Requirements - PHY SDR Mode
                3.           301
                4.           OSPI Switching Characteristics - PHY SDR Mode
                5.           303
              2. 6.11.5.14.1.2.2 OSPI0 PHY DDR Timing
                1.           OSPI DLL Delay Mapping for PHY DDR Timing Modes
                2.           OSPI Timing Requirements - PHY DDR Mode
                3.           307
                4.           OSPI Switching Characteristics - PHY DDR Mode
                5.           309
          3. 6.11.5.14.2 OSPI0 Tap Mode
            1. 6.11.5.14.2.1 OSPI0 Tap SDR Timing
              1.          OSPI Timing Requirements - Tap SDR Mode
              2.          313
              3.          OSPI Switching Characteristics - Tap SDR Mode
              4.          315
            2. 6.11.5.14.2.2 OSPI0 Tap DDR Timing
              1.          OSPI Timing Requirements - Tap DDR Mode
              2.          318
              3.          OSPI Switching Characteristics - Tap DDR Mode
              4.          320
        15. 6.11.5.15 Timers
          1.        Timer Timing Conditions
          2.        Timer Timing Requirements
          3.        Timer Switching Characteristics
          4.        325
        16. 6.11.5.16 UART
          1.        UART Timing Conditions
          2.        UART Timing Requirements
          3.        UART Switching Characteristics
          4.        330
        17. 6.11.5.17 USB
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Processor Subsystems
      1. 7.3.1 Arm Cortex-R5F Subsystem
      2. 7.3.2 Device/Power Manager
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 Power Supply
      2. 8.1.2 External Oscillator
      3. 8.1.3 JTAG, EMU, and TRACE
      4. 8.1.4 Unused Pins
    2. 8.2 Peripheral- and Interface-Specific Design Information
      1. 8.2.1 OSPI/QSPI/SPI Board Design and Layout Guidelines
        1. 8.2.1.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
        2. 8.2.1.2 External Board Loopback
        3. 8.2.1.3 DQS (only available in Octal SPI devices)
      2. 8.2.2 High Speed Differential Signal Routing Guidance
      3. 8.2.3 Thermal Solution Guidance
    3. 8.3 Clock Routing Guidelines
      1. 8.3.1 Oscillator Routing
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
  • ANJ|361
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Device Comparison

Table 4-1 shows a comparison between devices, highlighting the differences.

Note: Availability of features listed in this table are a function of shared IO pins, where IO signals associated with many of the features are multiplexed to a limited number of pins. The SysConfig tool should be used to assign signal functions to pins. This will provide a better understanding of limitations associated with pin multiplexing.
Table 4-1 Device Comparison
FEATURES REFERENCE
NAME		 AM27542 AM27522 AM27521
JTAG Device ID TBD
PROCESSORS AND ACCELERATORS
Speed Grades See Operating Performance Points
Arm Cortex-R5F in MAIN domain R5FSS Quad Core Dual Core
Device Management Subsystem WKUP_R5F Single Core
Hardware Security Module HSM Yes
Crypto Accelerators Security Yes
C7x Floating Point, Vector DSP C7x256V DSP Dual Core Single Core
Asynchronous Audio Sample Rate Converter ASRC Two One
SAFETY AND SECURITY
AEC-Q100 Qualified Q1 Yes(1)
PROGRAM AND DATA STORAGE
On-Chip Shared Memory (RAM) OCSRAM Up to 6MB(2) see Device Naming Convention
R5F Tightly Coupled Memory (TCM) TCM 256KB
PERIPHERALS
Modular Controller Area Network Interface with Full CAN-FD MCAN 5
General-Purpose I/O GPIO Up to 177 (up to 21 IO Retention capable)
Inter-Integrated Circuit Interface I2C 8(3)
Multichannel Audio Serial Port MCASP 5
Multichannel Serial Peripheral Interface MCSPI 5
Multi-Media Card/Secure Digital Interface MMC/SD 1x eMMC (8-bits) or 1x SD/SDIO (4-bits)
Flash Subsystem (FSS)(4) OSPI/QSPI FSS0 additionally supports OptiFlash, FOTA, and FLC
FSS1 additionally supports HyperRAM
Gigabit Ethernet Interface CPSW3G 2 Ports (RGMII/RMII)
General-Purpose Timers TIMER 22 (16 in Main, 2 in WKUP, 4 in Security)
Enhanced Pulse-Width Modulator Module EPWM 3
Enhanced Capture Module ECAP 6
Universal Asynchronous Receiver and Transmitter UART 8(5)
USB2.0 Controller with PHY USB 2.0 1
Analog-to-Digital Converter ADC 1
Media Local Bus (MOST50) MLB 1
(1) AEC-Q100 qualification is applicable to select part number variants as indicated by the Automotive Designator (Q1) identifier in the Device Naming Convention.
(2) Exact amount of On-Chip SRAM depends on the part number variant as indicated by the SRAM Memory (f) identifier in theDevice Naming Convention .
(3) 7x I2C instances are in the MAIN domain. 1x I2C instance is in the WKUP domain.
(4) Two flash interfaces, independently configured as OSPI or QSPI. FSS0 supports OptiFlash, FOTA and and FLC, FSS1 supports HyperRAM, and both FSS0 and FSS1 support XIP.
(5) 7x UART instances are in the MAIN domain. 1x UART instance is in the WKUP domain..