SPRS681G October 2010 – March 2015 AM3892 , AM3894
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The device has the following voltage domains:
These domains define groups of modules that share the same supply voltage for their core logic. Each voltage domain is powered by dedicated supply voltage rails. For the mapping between voltage domains and the supply pins associated with each, see Table 4-33.
Note: A regulated supply voltage must be supplied to each voltage domain at all times, regardless of the power domain states.
The device's 1-V AVS and 1-V constant voltage domains have seven power domains that supply power to both the core logic and SRAM within their associated modules. All other voltage domains have only always-on power domain.
Within the 1-V AVS and 1-V constant voltage domains, each power domain, except for the always-on domain, has an internal power switch that can completely remove power from that domain. At power-up, all domains, except always-on, come-up as power gated. Since there is an always-on domain in each voltage domain, all power supplies are expected to be ON all the time (as long as the device is in use).
For details on powering up or powering down the device power domains, see the AM389x Sitara ARM Processors Technical Reference Manual (SPRUGX7).
Note: All modules within a power domain are unavailable when the domain is powered OFF. For instructions on powering ON or powering OFF the domains, see the AM389x Sitara ARM Processors Technical Reference Manual (SPRUGX7).
This domain contains the SGX530 (available only on the AM3894 device).
The active domain has all modules that are only needed when the system is in "active" state. In any of the standby states, these modules are not needed. This domain contains the HDVPSS peripheral.
The default domain contains modules that might be required even in standby mode. Having them in a separate power domain allows customers to power gate these modules when in standby mode. This domain has the DDR, SATA, PCIe, Media Controller and USB peripherals.
The always-on domain contains all modules that are required even when the system goes to standby mode. This includes the host ARM and modules that generate wake-up interrupts (for example, UART, RTC, GPIO, EMAC) as well as other low-power IOs.
The device contains SmartReflex modules that are required to minimize power consumption on the voltage domains using external variable-voltage power supplies. Based on the device process, temperature, and desired performance, the SmartReflex modules advise the host processor to raise or lower the supply voltage to each domain for minimal power consumption. The communication link between the host processor and the external regulators is a system-level decision and can be accomplished using GPIOs or I2C.
The major technique employed by SmartReflex in the device is adaptive voltage scaling (AVS). Based on the silicon process and temperature, the SmartReflex modules guide software in adjusting the core 1-V supply voltage within the desired range. This technique is called adaptive voltage scaling (AVS). AVS occurs continuously and in real time, helping to minimize power consumption in response to changing operating conditions.
NOTE
Implementation of SmartReflex AVS is required for proper device operation.
The device memories offer three different modes to save power when memories are not being used; Table 8-1 provides the details.
MODE | POWER SAVING | WAKE-UP LATENCY | MEMORY CONTENTS |
---|---|---|---|
Light Sleep (LS) | ~60% | Low | Preserved |
Deep Sleep (DS) | ~75% | Medium | Preserved |
Shut Down (SD) | ~95% | High | Lost |
The device provides a feature that allows the software to put the chip-level memories (OCMC RAMs) in any of the three (LS, DS, and SD) modes. There are control registers in the control module to control the power-down state of OCMC RAM0 and OCMC RAM1. There are also status registers that can be used during power-up to check if memories are powered-up. For detailed instructions on entering and exiting from light sleep and deep sleep modes, see the AM389x Sitara ARM Processors Technical Reference Manual (SPRUGX7).
Memories inside switchable domains go to the shut down (SD) state whenever the power domain goes to the OFF state. Memories come back to functional state along with the domain power-up.
In order to reduce SRAM leakage, many SRAM blocks can be switched from active mode to shut-down mode. When SRAM is put in shut-down mode, the voltage supplied to it is automatically removed and all data in that SRAM is lost.
All SRAM located in a switchable power domain (all domains except always-on) automatically enters shut-down mode whenever its assigned associated power domain goes to the OFF state. The SRAM returns to the active state when the corresponding power domain returns to the ON state.
For detailed instructions on powering up or powering down the various device SRAM, see the AM389x Sitara ARM Processors Technical Reference Manual (SPRUGX7).
The DDR3 IOs are put into power-down mode automatically when the default power domain is turned OFF.
The HDMI PHY controller is in the always-on power domain, so software must configure the PHY into power-down mode.
There is no power-down mode for the other 3.3-V IOs.
The device power supplies must be sequenced in the following order:
Each supply (represented by VDDB in Figure 8-1) must begin actively ramping between 0 ms and 50 ms after the previous supply (represented by VDDA in Figure 8-1) in the sequence has reached 80% of its nominal value, as shown in Figure 8-1.
NOTE
The device pins are not fail-safe. Device pins should not be externally driven before the corresponding supply rail has been powered up. The corresponding supply rail for each pin can be found in Section 4.2, Terminal Functions.
Recommended capacitors for power supply decoupling are all 0.1 µF in the smallest body size that can be used. Capacitors are more effective in the smallest physical size to limit lead inductance. For example, 0402 sized capacitors are better than 0603 sized capacitors, and so on.
SUPPLY | MINIMUM CAPACITOR NO. |
---|---|
VDDA_PLL | 2(1) |
DVDD1P8 | 2 |
VDDT_SATA | 2(1) |
VDDT_PCIE | 3(1) |
CVDDC | 20(2) |
DVDD_3p3 | 64(2) |
CVDD | 28(2) |
DDR-related supply capacitor numbers are provided in Section 9.3.
The device has several types of system-level resets. Table 8-3 lists these reset types, along with the reset initiator and the effects of each reset on the device.
TYPE | INITIATOR | RESETS ALL MODULES, EXCLUDING EMULATION | RESETS EMULATION | LATCHES BOOT PINS | ASSERTS RSTOUT PIN |
---|---|---|---|---|---|
Power-On Reset (POR) | POR pin | Yes | Yes | Yes | Yes |
External Warm Reset | RESET pin | Yes | No | Yes | Yes |
Emulation Warm Reset | On-Chip Emulation Logic | Yes | No | No | Yes |
Watchdog Reset | Watchdog Timer | Yes | No | No | Yes |
Software Global Cold Reset | Software | Yes | Yes | No | Yes |
Software Global Warm Reset | Software | Yes | No | No | Yes |
Test Reset | TRST pin | No | Yes | No | No |
Power-on reset (POR) is initiated by the POR pin and is used to reset the entire chip, including the test and emulation logic. POR is also referred to as a cold reset since it is required to be asserted when the devices goes through a power-up cycle. However, a device power-up cycle is not required to initiate a power-on reset.
The following sequence must be followed during a power-on reset:
An external warm reset is activated by driving the RESET pin active-low. This resets everything in the device, except the ARM Cortex-A8 interrupt controller, test, and emulation. An emulator session stays alive during warm reset.
The following sequence must be followed during a warm reset:
An emulation warm reset is activated by the on-chip emulation module. It has the same effect and requirements as an external warm reset (RESET), with the exception that it does not re-latch the BOOT pins.
The emulator initiates an emulation warm reset via the ICEPick module. To invoke the emulation warm reset via the ICEPick module, the user can perform the following from the Code Composer Studio™ IDE menu:
Debug → Advanced Resets → System Reset.
A watchdog reset is initiated when the watchdog timer counter reaches zero. It has the same effect and requirements as an external warm reset (RESET), with the exception that it does not re-latch the BOOT pins. In addition, a watchdog reset always results in RSTOUT being asserted.
A software global cold reset is initiated under software control. It has the same effect and requirements as a power-on reset (POR), with the exception that it does not re-latch the BOOT pins.
Software initiates a software global cold reset by writing to RST_GLOBAL_COLD_SW in the PRM_RST_CTRL register.
A software global warm reset is initiated under software control. It has the same effect and requirements as a external warm reset (RESET), with the exception that it does not re-latch the BOOT pins.
Software initiates a software global warm reset by writing to RST_GLOBAL_WARM_SW in the PRM_RST_CTRL register.
A test reset is activated by the emulator asserting the TRST pin. The only effect of a test reset is to reset the emulation logic.
The local reset for various modules within the device is controlled by programming the PRCM and the module's internal registers. Only the associated module is reset when a local reset is asserted, leaving the rest of the device unaffected.
For details on local reset, see the PRCM chapter of the AM389x Sitara ARM Processors Technical Reference Manual (SPRUGX7) and individual subsystem and peripheral user's guides.
If any of the above reset sources occur simultaneously, the device only processes the highest-priority reset request. The reset request priorities, from high to low, are as follows:
The Reset Status Register (PRM_RSTST) contains information about the last reset that occurred in the system. For more information on this register, see the PRCM chapter of the AM389x Sitara ARM Processors Technical Reference Manual (SPRUGX7).
The device supports reset isolation for the PCI Express (PCIe) module. This means that the PCI Express subsystem can be reset without resetting the rest of the device.
When the device is a PCI Express Root Complex (RC), the PCIe subsystem can be reset by software through the PRCM. Software should ensure that there are no ongoing PCIe transactions before asserting this reset by first taking the PCIe subsystem into the IDLE state by programming the register CM_DEFAULT_PCI_CLKCTRL inside the PRCM. After bringing the PCIe subsystem out of reset, bus enumeration should be performed again and should treat all endpoints (EP) as if they had just been connected.
When the device is a PCI Express Endpoint (EP), the PCIe subsystem generates an interrupt when an in-band reset is received. Software should process this interrupt by putting the PCIe subsystem in the IDLE state and then asserting the PCIe local reset through the PRCM.
All device-level resets mentioned in the previous sections, except Test Reset, also reset the PCIe subsystem. Therefore, the device should issue a Hot Reset to all downstream devices and re-enumerate the bus upon coming out of reset.
The RSTOUT pin on the device reflects device reset status and is de-asserted (high) when the device is out of reset. In addition, this output is always 3-stated and the internal pull resistor is disabled on this pin while POR or RESET is asserted; therefore, an external pullup or pulldown can be used to set the state of this pin (high or low) while POR or RESET is asserted. For more detailed information on external pullups and pulldowns, see Section 6.3.1. This output is always asserted low when any of the following resets occur:
The RSTOUT pin remains asserted until PRCM releases the host ARM Cortex-A8 processor for reset.
The device emulation and trace is only reset by the following sources:
Other than these three, none of the other resets affect emulation and trace functionality.
Each power domain has a dedicated warm reset and cold reset. Warm reset for a power domain is asserted under either of the following two conditions:
Cold reset for a power domain is asserted under either of the following two conditions:
When any reset (other than test reset) described in Section 8.2.1 is asserted, all device pins are put into a Hi-Z state except for:
In addition, the PINCNTL registers, which control pin multiplexing, slew control, enabling the pullup or pulldown, and enabling the receiver, are reset to the default state. For a description of the RESET_ISO register, see the AM389x Sitara ARM Processors Technical Reference Manual (SPRUGX7).
Internal pullup or pulldown (IPU or IPD) resistors are enabled during and immediately after reset as described in the OTHER column in the tables in Section 4.2, Terminal Functions.
NOTE
If a configuration pin must be routed out from the device, the internal pullup or pulldown (IPU or IPD) resistor should not be relied upon; TI recommends the use of an external pullup or pulldown resistor.
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
1 | tw(RESET) | Pulse duration, POR low or RESET low | 32C(1) | ns | |
2 | tsu(CONFIG) | Setup time, boot and configuration pins valid before POR high or RESET high(2) | 12C(1) | ns | |
3 | th(CONFIG) | Hold time, boot and configuration pins valid after POR high or RESET high(2) | 0 | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
tw(RSTL) | Pulse width, RESET low | 10C(1) | ns | ||
4 | td(RSTL_IORST) | Delay time, RESET falling to all IO entering reset state | 0 | 14 | ns |
5 | td(RSTL_IOFUNC) | Delay time, RESET rising to IO exiting reset state | 0 | 14 | ns |
The device clocks are generated from several external reference clocks that are fed to on-chip PLLs and dividers (both inside and outside of the PRCM Module). Figure 8-4 shows a high-level overview of the device clocking structure. Note that to reduce complexity, all clocking connections are not shown. For detailed information on the device clocks, see the Device Clocking and Flying Adder PLL section of the AM389x Sitara ARM Processors Technical Reference Manual (SPRUGX7).
The device has four on-chip PLLs and one reference clock which are generated by on-chip oscillators. In addition to the 27-MHz reference clock, a 100-MHz differential clock input is required for SATA and PCIe. A third clock input is an optional 32.768-kHz clock input (no on-chip oscillator) for the RTC.
The device clock input (DEV_MXI and DEV_CLKIN) is used to generate the majority of the internal reference clocks. An external square-wave clock can be supplied to DEV_CLKIN instead of using a crystal input. The device clock should be 27 MHz.
Section 8.3.1.1 provides details on using the on-chip oscillators with external crystals for the 27-MHz system oscillator.
When the internal oscillators are used to generate the device clock, external crystals are required to be connected across the MXI and MXO pins, along with two load capacitors, as shown in Figure 8-5. The external crystal load capacitors should also be connected to the associated oscillator ground pin (DEVOSC_VSS). The capacitors should not be connected to board ground (VSS).
The load capacitors, C1 and C2 in Figure 8-5, should be chosen such that the equation below is satisfied. CL in the equation is the load specified by the crystal manufacturer. Rd is an optional damping resistor. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator MXI, MXO, and VSS pins.
PARAMETER | MIN | NOM | MAX | UNIT |
---|---|---|---|---|
Start-up time (from power up until oscillating at stable frequency of 27 MHz) | 4 | ms | ||
Crystal Oscillation frequency | 27 | MHz | ||
Parallel Load Capacitance (C1 and C2) | 12 | 24 | pF | |
Crystal ESR | 60 | Ohm | ||
Crystal Shunt Capacitance | 5 | pF | ||
Crystal Oscillation Mode | Fundamental Only | |||
Crystal Frequency stability | ±50 | ppm |
NO. | MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|---|
1 | tc(DCK) | Cycle time, DEV_CLKIN | 37.037 | ns | ||
2 | tw(DCKH) | Pulse duration, DEV_CLKIN high | 0.45C | 0.55C | ns | |
3 | tw(DCKL) | Pulse duration, DEV_CLKIN low | 0.45C | 0.55C | ns | |
4 | tt(DCK) | Transition time, DEV_CLKIN | 7 | ns | ||
5 | tJ(DCK) | Period jitter, DEV_CLKIN (VDACs not used) | 150 | ps | ||
Period jitter, DEV_CLKIN (VDACs used) | A | s | ||||
Sf | Frequency stability, DEV_CLKIN | ±50 | ppm |
A high-quality, low-jitter differential clock source is required for the PCIe and SATA PHYs. The clock is required to be AC coupled to the device's SERDES_CLKP and SERDES_CLKN pins according to the specifications in Table 8-11. Both the clock source and the coupling capacitors should be placed physically as close as possible to the processor.
When the PCIe interface is used, the SERDES_CLKN or SERDES_CLKP clock is required to meet the REFCLK AC specifications outlined in the PCI Express Card Electromechanical Specification (Gen.1 and Gen.2). When the SATA interface is used, the SERDES_CLKN or SERDES_CLKP clock is required to meet the specifications in Table 8-8. When both the PCIe and SATA interfaces are used, both sets of specifications must be met simultaneously.
PARAMETER | MIN | TYP | MAX | UNIT |
---|---|---|---|---|
Clock Frequency | 100 | MHz | ||
Jitter | 50 | Ps pk-pk | ||
Duty Cycle | 40 | 60 | % | |
Rise and Fall Time | 700 | ps |
An HCSL differential clock source is required to meet the REFCLK AC specifications outlined in the PCI Express Card Electromechanical Specification, Rev. 2.0, at the input to the AC coupling capacitors. In addition, LVDS clock sources that are compliant to the above specification, but with the exceptions shown in Table 8-9, are also acceptable.
SYMBOL | PARAMETER | MIN | MAX | UNIT |
---|---|---|---|---|
VIH | Differential input high voltage (VIH) | 125 | 1000 | mV |
VIL | Differential input high voltage (VIL) | -1000 | -125 | mV |
PARAMETER | MIN | TYP | MAX | UNIT |
---|---|---|---|---|
Number of stubs allowed on SERDES_CLKN and SERDES_CLKP traces | 0 | Stubs | ||
SERDES_CLKN and SERDES_CLKP trace length from oscillator to device | 24000(1) | Mils | ||
SERDES_CLKN and SERDES_CLKP pair differential impedance | 100 | Ohms | ||
Number of vias on each SERDES_CLKN and SERDES_CLKP trace(2) | 3 | Vias | ||
SERDES_CLKN and SERDES_CLKP differential pair to any other trace spacing | 2*DS(3) |
AC coupling capacitors are required on the SERDES_CLKN and SERDES_CLKP pair. Table 8-11 shows the requirements for these capacitors.
PARAMETER | MIN | TYP | MAX | UNIT |
---|---|---|---|---|
SERDES_CLKN and SERDES_CLKP AC coupling capacitor value(1) | 0.24 | 0.27 | 4 | nF |
SERDES_CLKN and SERDES_CLKP AC coupling capacitor package size | 0402 | 10 Mils(2)(3) |
An external 32.768-kHz clock input can optionally be provided at the CLKIN32 pin to serve as a reference clock in place of the RTCDIVIDER clock for the RTC and Timer modules. If the CLKIN32 pin is not connected to a 32.768-kHz clock input, this pin should be pulled low. The CLKIN32 source must meet the timing requirements shown in Table 8-12.
NO. | MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|---|
1 | tc(CLKIN32) | Cycle time, CLKIN32 | 1/32768 | s | ||
2 | tw(CLKIN32H) | Pulse duration, CLKIN32 high | 0.45C | 0.55C | ns | |
3 | tw(CKIN32L) | Pulse duration, CLKIN32 low | 0.45C | 0.55C | ns | |
4 | tt(CLKIN32) | Transition time, CLKIN32 | 7 | ns | ||
5 | tJ(CLKIN32) | Period jitter, CLKIN32 | 0.02C | ns |
The device contains four embedded PLLs (Main, Audio, Video and DDR) that provide clocks to different parts of the system. For a high-level view of the device clock architecture, including the PLL reference clock sources and connections, see Figure 8-4.
The reference clock for most of the PLLs comes from the DEV_CLKIN input clock. Also, each PLL supports a bypass mode in which the reference clock can be directly passed to the PLL CLKOUT. All device PLLs (except the DDR PLL) come-up in bypass mode after reset.
Flying-adder PLLs are used for all the on-chip PLLs. Figure 8-8 shows the basic structure of the flying-adder PLL.
The flying-adder PLL has two main components: a multi-phase PLL and the flying-adder synthesizer. The multi-phase PLL takes an input reference clock (fr), multiplies it with factor, N, and provides a K-phase output to the flying-adder synthesizer. The flying-adder synthesizer takes this multi-phase clock input and produces a variable frequency clock (fs). There can be a post divider on this clock which takes in clock fs and drives out clock fo. The frequency of the clock driven out is given by:
There can be multiple flying-adder synthesizers attached to one multi-phase PLL to generate different frequencies. In this case, FREQ (4 bits of integer and 24 bits of fractional value) and M (1 to 255) values can be adjusted for each clock separately, based on the frequency needed. The multi-phase PLL used in this device has a value of K = 8.
For details on programming the device PLLs, see the PLL chapter of the AM389x Sitara ARM Processors Technical Reference Manual (SPRUGX7).
The PLL and Flying Adder Synthesizers support generation of a wide range of clocks that are all generated from the same input clock source. Therefore, these clocks are all synchronous. The flying-adder synthesizers take the multi-phase clock from the PLL and produce variable frequency clocks (fs) as stated in the previous section. Each variable frequency clock is then divided by a post divider before use.
The clock outputs from the PLL, Synthesizer and Post Divider contain period variations that must be considered. The minimum period of the generated clock is effectively the maximum clock rate. Different configurations of the PLL dividers, Synthesizer and output dividers will have larger or smaller amounts of phase variation. The equation below will calculate the minimum cycle period for a given set of settings. The result of the following minimum cycle equation must be greater than the value shown in Table 8-13.
The first term of the below equation is a characteristic of the Flying Adder PLL. The selection of M*FREQ is important. Choosing a non-integer value of M*FREQ will cause larger period variation and a higher peak instantaneous frequency. Use of non-integer M*FREQ can be done to create specific average frequencies at the cost of higher phase variation. Using integer values of M*FREQ result in minimum phase variation. The second and third terms are PLL phase jitter terms associated with the frequency synthesis. The second term is about 20ps and the third is normally 10ps.
Please refer to the Technical Reference Manual (SPRUGX7) for examples using this equation. The TRM also contains a standard set of configurations that we recommend for customer use.
Where:
CLOCK | DEVICE SPEED RANGE | MIN CYCLE (ps) |
---|---|---|
Main PLL | ||
Clock 2 | Blank | 1000 |
2 | 833 | |
4 | 741 | |
Clock 3 | Blank | 1876 |
2 | 1667 | |
4 | 1481 | |
Clock 4 | Blank | 2000 |
2 | 1786 | |
4 | 1667 | |
DDR PLL | ||
Clock 2 | Blank, 2, 4 | 18519 |
Clock 3 | Blank | 2632 |
2 | 2632 | |
4 | 2222 | |
Video PLL | ||
Clock 1 | Blank, 2, 4 | 1515 |
Clock 2 | Blank, 2, 4 | 1515 |
Clock 3 | Blank, 2, 4 | 1515 |
Audio PLL | ||
Clock 2 | Blank, 2, 4 | 6329 |
Clock 3 | Blank, 2, 4 | 5076 |
Clock 4 | Blank, 2, 4 | 5076 |
Clock 5 | Blank, 2, 4 | 5076 |
The device PLLs are supplied externally via the VDDA_PLL power-supply pins. External filtering must be added on the PLL supply pins to ensure that the requirements in Table 8-14 are met.
PARAMETER | MIN | MAX | UNIT |
---|---|---|---|
Dynamic noise at VDDA_PLL pins | 50 | mV p-p |
All of the flying-adder PLLs (except the DDR PLL) come-up in bypass mode at reset. All of the registers (P, N, FREQ, and M) need to be programmed appropriately and then wait approximately 8 µs for PLL_Audio and 5 µs for the other PLLS to be locked. Verification that the PLL is locked can be checked by accessing the lock status bit in the PLL control register for each PLL (bit = 1 when the PLL is locked). Once the PLL is locked, then the FA-PLL can be taken out of bypass mode. Control for bypass mode is through chip-level registers. For more details on the PLL registers and bypass logic, see the PLL chapter of the AM389x Sitara ARM Processors Technical Reference Manual (SPRUGX7).
The PLL control registers reside in the control module and are listed in Table 6-3.
In some cases, the system clock inputs and PLL outputs are sent to the PRCM module for division and multiplexing before being routed to the various device modules. These clock outputs from the PRCM module are called SYSCLKs. Table 8-15 lists the main device SYSCLKs along with their maximum supported clock frequencies. In addition, limits shown in the table may be further restricted by the clock frequency limitations of the device modules using these clocks. For more details on module clock frequency limits, see Section 8.3.6.
SYSCLK | PLL Type | DEVICE SPEED RANGE(1) | MAXIMUM FREQUENCY (MHz)(2) | DESTINATION |
---|---|---|---|---|
SYSCLK2 | Main | Blank | 930 | To ARM Cortex-A8 |
2 | 1100 | |||
4 | 1200 | |||
SYSCLK3 | Main | Blank | 500 | To HDVICP2s |
2 | 550 | |||
4 | 630 | |||
SYSCLK4 | Main | Blank | 460 | L3, OCP clock for HDVPSS, TPTCs, TPCC, DMM, Unicache clock for Media Controller, EDMA |
2 | 550 | |||
4 | 570 | |||
SYSCLK5 | Main | Blank | 230 | L3, L4_HS, OCP clock for EMAC, SATA, PCIe, Media Controller, OCMC RAM |
2 | 275 | |||
4 | 285 | |||
SYSCLK6 | Main | Blank | 115 | L3, L4_STD, UART, I2C, SPI, SD, SDIO, TIMER, GPIO, PRCM, McASP, McBSP, GPMC, ELM, HDMI, WDT, Mailbox, RTC, Spinlock, SmartReflex and USB |
2 | 137 | |||
4 | 143 | |||
SYSCLK7 | Main | Blank | 90 | Reserved |
2 | 110 | |||
4 | 115 | |||
SYSCLK8 | Main | Blank | 364 | DMM, DDR OCP clock |
2 | 364 | |||
4 | 425 | |||
SYSCLK9 | DDR | Blank, 2, 4 | 16 | CEC clock, VTP |
SYSCLK10 | DDR | Blank, 2, 4 | 48 | SPI, I2C, SDIO, and UART functional clock |
SYSCLK11 | Video | Blank, 2, 4 | 216 | Reserved |
SYSCLK13 | Video | Blank, 2, 4 | 165 | HDVPSS |
SYSCLK14 | Video | Blank, 2, 4 | 27 | Reserved |
SYSCLK15 | Video | Blank, 2, 4 | 165 | HDVPSS |
SYSCLK16 | Video | Blank, 2, 4 | 27 | Reserved |
SYSCLK17 | Video | Blank, 2, 4 | 54 | HDVPSS |
SYSCLK18 | Audio | Blank, 2, 4 | 32 KHz | RTC |
SYSCLK19 | Audio | Blank, 2, 4 | 160 | Reserved |
SYSCLK20 | Audio | Blank, 2, 4 | 196 | Audio clock 1 |
SYSCLK21 | Audio | Blank, 2, 4 | 196 | Audio clock 2 |
SYSCLK22 | Audio | Blank, 2, 4 | 196 | Audio clock 3 |
SYSCLK23 | Main | Blank | 310 | SGX530 OCP clock |
2 | 275 | |||
4 | 300 | |||
SYSCLK24 | Main | Blank, 2, 4 | 125 | GMII clock |
Device modules receive their clock directly from an external clock input, directly from a PLL, or from a PRCM SYSCLK output. Table 8-16 lists the clock source options for each module, along with the maximum frequency that module can accept. The device PLLs and dividers must be programmed not to exceed the maximum frequencies listed in this table to ensure proper module functionality.
MODULE | CLOCK SOURCES | DEVICE SPEED RANGE(1) | MAX. FREQUENCY (MHz)(2) |
---|---|---|---|
Cortex-A8 | SYSCLK2 | Blank | 930 |
2 | 1100 | ||
4 | 1200 | ||
DMM | SYSCLK4 | Blank | 460 |
2 | 550 | ||
4 | 570 | ||
DMM, DDR OCP | SYSCLK8 | Blank | 364 |
2 | 364 | ||
4 | 425 | ||
EDMA | SYSCLK4 | Blank | 460 |
2 | 550 | ||
4 | 570 | ||
ELM | SYSCLK6 | Blank | 115 |
2 | 137 | ||
4 | 143 | ||
EMAC | SYSCLK5 | Blank | 230 |
2 | 275 | ||
4 | 285 | ||
GPIO0 and GPIO1 | SYSCLK6 | Blank | 115 |
2 | 137 | ||
4 | 143 | ||
SYSCLK18 | Blank, 2, 4 | 32.768 KHz | |
GPMC | SYSCLK6 | Blank | 115 |
2 | 137 | ||
4 | 143 | ||
HDMI | SYSCLK6 | Blank | 115 |
2 | 137 | ||
4 | 143 | ||
HDMI CEC | SYSCLK9 | Blank, 2, 4 | 16 |
HDVICP2-0, HDVICP2-1, HDVICP2-2 | SYSCLK3 | Blank | 500 |
2 | 550 | ||
4 | 630 | ||
HDVPSS VPDMA | SYSCLK4 | Blank | 460 |
2 | 550 | ||
4 | 570 | ||
HDVPSS | SYSCLK5 | Blank | 230 |
2 | 275 | ||
4 | 285 | ||
HDVPSS Interface | SYSCLK6 | Blank | 115 |
2 | 137 | ||
4 | 143 | ||
HDVPSS HD VENCD | SYSCLK13 | Blank, 2, 4 | 165 |
HDVPSS HD VENCA | SYSCLK15 | Blank, 2, 4 | 165 |
HDVPSS SD VENC | SYSCLK17 | Blank, 2, 4 | 54 |
I2C0, I2C1 | SYSCLK6 | Blank | 115 |
2 | 137 | ||
4 | 143 | ||
SYSCLK10 | Blank, 2, 4 | 48 | |
L3 | SYSCLK4 | Blank | 460 |
2 | 550 | ||
4 | 570 | ||
L3 | SYSCLK5 | Blank | 230 |
2 | 275 | ||
4 | 285 | ||
L3 | SYSCLK6 | Blank | 115 |
2 | 137 | ||
4 | 143 | ||
L4 HS | SYSCLK5 | Blank | 230 |
2 | 275 | ||
4 | 285 | ||
L4 STD | SYSCLK6 | Blank | 115 |
2 | 137 | ||
4 | 143 | ||
Mailbox | SYSCLK6 | Blank | 115 |
2 | 137 | ||
4 | 143 | ||
McASP0, McASP1, McASP2 | SYSCLK6 | Blank, 2, 4 | 125 |
McBSP | SYSCLK6 | Blank, 2, 4 | 125 |
Media Controller | SYSCLK5 | Blank | 230 |
2 | 275 | ||
4 | 285 | ||
System MMU | SYSCLK4 | Blank | 460 |
2 | 550 | ||
4 | 570 | ||
OCMC RAM | SYSCLK5 | Blank | 230 |
2 | 275 | ||
4 | 285 | ||
PCIe | SYSCLK5 | Blank | 230 |
2 | 275 | ||
4 | 285 | ||
RTC | SYSCLK6 | Blank | 115 |
2 | 137 | ||
4 | 143 | ||
SYSCLK18 | Blank, 2, 4 | 32.768 KHz | |
SATA | SYSCLK5 | Blank | 230 |
2 | 275 | ||
4 | 285 | ||
SD, SDIO | SYSCLK6 | Blank | 115 |
2 | 137 | ||
4 | 143 | ||
SYSCLK10 | Blank, 2, 4 | 48 | |
SGX530 | SYSCLK23 | Blank | 310 |
2 | 275 | ||
4 | 300 | ||
SmartReflex | SYSCLK6 | Blank | 115 |
2 | 137 | ||
4 | 143 | ||
SPI | SYSCLK6 | Blank | 115 |
2 | 137 | ||
4 | 143 | ||
SYSCLK10 | Blank, 2, 4 | 48 | |
Spinlock | SYSCLK6 | Blank | 115 |
2 | 137 | ||
4 | 143 | ||
Timers, WDT | SYSCLK6 | Blank | 115 |
2 | 137 | ||
4 | 143 | ||
SYSCLK18 | Blank, 2, 4 | 32.768 KHz | |
UART0, UART1, UART2 | SYSCLK6 | Blank | 115 |
2 | 137 | ||
4 | 143 | ||
SYSCLK10 | Blank, 2, 4 | 48 | |
USB0, USB1 | SYSCLK6 | Blank | 115 |
2 | 137 | ||
4 | 143 |
The device includes one selectable general-purpose clock output (CLKOUT). The source for these output clocks is controlled by the CLKOUT_MUX register in the control module and shown in Figure 8-9.
As shown in the figure, there are four possible sources for CLKOUT, one clock from each of the four PLLs. The selected clock can be further divided by any ratio from 1 to 1/8 before going out on the CLKOUT pin. The default selection is to select main PLL clock5, divider set to 1/1, and clock disabled.
NO. | PARAMETER | MIN | MAX | UNIT | ||
---|---|---|---|---|---|---|
1 | tc(CLKOUT) | Cycle time, CLKOUT | 10 | ns | ||
2 | tw(CLKOUTH) | Pulse duration, CLKOUT high | 0.45P | 0.55P | ns | |
3 | tw(CLKOUTL) | Pulse duration, CLKOUT low | 0.45P | 0.55P | ns | |
4 | tt(CLKOUT) | Transition time, CLKOUT | 0.05P | ns |
The device has a large number of interrupts. It also has the ARM Cortex™-A8 master capable of servicing interrupts. Specific details, such as the processing flow, configuration steps, and interrupt controller registers, for each of these masters are found in their respective subsystem documentation.
Table 8-18 lists all the device interrupts by module and indicates the interrupt destination: ARM Cortex™-A8.
MODULE | INTERRUPT | DESTINATION | DESCRIPTION |
---|---|---|---|
Cortex™-A8 | |||
Serial ATA | INTRQ | SATA Module interrupt | |
INTRQ_PEND_N | X | ||
EMAC SS0 | C0_RX_THRESH_INTR_REQ | Receive threshold (non paced) | |
C0_RX_THRESH_INTR_PEND | X | ||
C0_RX_INTR_REQ | Receive pending interrupt (paced) | ||
C0_RX_INTR_PEND | X | ||
C0_TX_INTR_REQ | Transmit pending interrupt (paced) | ||
C0_TX_INTR_PEND | X | ||
C0_MISC_INTR_REQ | Stat, Host, MDIO LINKINT or MDIO USERINT | ||
C0_MISC_INTR_PEND | X | ||
EMAC SS1 | C0_RX_THRESH_INTR_REQ | Receive threshold (non paced) | |
C0_RX_THRESH_INTR_PEND | X | ||
C0_RX_INTR_REQ | Receive pending interrupt (paced) | ||
C0_RX_INTR_PEND | X | ||
C0_TX_INTR_REQ | Transmit pending interrupt (paced) | ||
C0_TX_INTR_PEND | X | ||
C0_MISC_INTR_REQ | Stat, Host, MDIO LINKINT or MDIO USERINT | ||
C0_MISC_INTR_PEND | X | ||
USB2.0 SS | USBSS_INTR_REQ | Queue MGR or CPPI Completion interrupt | |
USBSS_INTR_PEND | X | ||
USB0_INTR_REQ | RX and TX DMA, Endpoint ready or error, or USB2.0 interrupt | ||
USB0_INTR_PEND | X | ||
USB1_INTR_REQ | |||
USB1_INTR_PEND | X | ||
SLV0P_SWAKEUP | X | USB wakeup | |
PCIe Gen2 | PCIE_INT_I_INTR0 | Legacy interrupt (RC mode only) | |
PCIE_INT_I_INTR_PEND_N0 | X | ||
PCIE_INT_I_INTR1 | MSI interrupt (RC mode only) | ||
PCIE_INT_I_INTR_PEND_N1 | X | ||
PCIE_INT_I_INTR2 | Error interrupt | ||
PCIE_INT_I_INTR_PEND_N2 | X | ||
PCIE_INT_I_INTR3 | Power Management interrupt | ||
PCIE_INT_I_INTR_PEND_N3 | X | ||
PCIE_INT_I_INTR4 | Reserved | ||
PCIE_INT_I_INTR_PEND_N4 | |||
PCIE_INT_I_INTR5 | |||
PCIE_INT_I_INTR_PEND_N5 | |||
PCIE_INT_I_INTR6 | |||
PCIE_INT_I_INTR_PEND_N6 | |||
PCIE_INT_I_INTR7 | |||
PCIE_INT_I_INTR_PEND_N7 | |||
PCIE_INT_I_INTR8 | |||
PCIE_INT_I_INTR_PEND_N8 | |||
PCIE_INT_I_INTR9 | |||
PCIE_INT_I_INTR_PEND_N9 | |||
PCIE_INT_I_INTR10 | |||
PCIE_INT_I_INTR_PEND_N10 | |||
PCIE_INT_I_INTR11 | |||
PCIE_INT_I_INTR_PEND_N11 | X | ||
PCIE_INT_I_INTR12 | |||
PCIE_INT_I_INTR_PEND_N12 | X | ||
PCIE_INT_I_INTR13 | |||
PCIE_INT_I_INTR_PEND_N13 | X | ||
PCIE_INT_I_INTR14 | |||
PCIE_INT_I_INTR_PEND_N14 | X | ||
PCIE_INT_I_INTR15 | |||
PCIE_INT_I_INTR_PEND_N15 | X | ||
SLE_IDLEP_SWAKEPUP | X | PCIe wakeup | |
TPCC | TPCC_INT_PO[0] | Region 0 DMA completion | |
TPCC_INT_PEND_N[0] | X | ||
TPCC_INT_PO[1] | Region 1 DMA completion | ||
TPCC_INT_PEND_N[1] | |||
TPCC_INT_PO[2] | Region 2 DMA completion | ||
TPCC_INT_PEND_N[2] | |||
TPCC_INT_PO[3] | Region 3 DMA completion | ||
TPCC_INT_PEND_N[3] | |||
TPCC_INT_PO[4] | Region 4 DMA completion | ||
TPCC_INT_PEND_N[4] | |||
TPCC_INT_PO[5] | Region 5 DMA completion | ||
TPCC_INT_PEND_N[5] | |||
TPCC_INT_PO[6] | Region 6 DMA completion | ||
TPCC_INT_PEND_N[6] | |||
TPCC_INT_PO[7] | Region 7 DMA completion | ||
TPCC_INT_PEND_N[7] | |||
TPCC_MPINT_PO | Memory protection error | ||
TPCC_MPINT_PEND_N | X | ||
TPCC_ERRINT_PO | TPCC error | ||
TPCC_ERRINT_PEND_N | X | ||
TPCC_INTG_PO | DMA Global completion | ||
TPCC_INTG_PEND_N | |||
TPTC 0 | TPTC_ERRINT_PO | TPTC0 error | |
TPTC_LERRINT_PO | X | ||
TPTC_INT_PO | TPTC0 completion | ||
TPTC_LINT_PO | |||
TPTC 1 | TPTC_ERRINT_PO | TPTC1 error | |
TPTC_LERRINT_PO | X | ||
TPTC_INT_PO | TPTC1 completion | ||
TPTC_LINT_PO | |||
TPTC 2 | TPTC_ERRINT_PO | TPTC2 error | |
TPTC_LERRINT_PO | X | ||
TPTC_INT_PO | TPTC2 completion | ||
TPTC_LINT_PO | |||
TPTC 3 | TPTC_ERRINT_PO | TPTC3 error | |
TPTC_LERRINT_PO | X | ||
TPTC_INT_PO | TPTC3 completion | ||
TPTC_LINT_PO | |||
DDR EMIF4d 0 | SYS_ERR_INTR | EMIF error | |
SYS_ERR_INTR_PEND_N | X | ||
DDR EMIF4d 1 | SYS_ERR_INTR | ||
SYS_ERR_INTR_PEND_N | X | ||
GPMC | GPMC_SINTERRUPT | X | GPMC interrupt |
UART 0 | NIRQ | X | UART and IrDA 0 interrupt |
UART 1 | NIRQ | X | UART and IrDA 1 interrupt |
UART 2 | NIRQ | X | UART and IrDA 2 interrupt |
Timer1 | POINTR_REQ | 32-bit Timer1 interrupt | |
POINTR_PEND | X | ||
Timer2 | POINTR_REQ | 32-bit Timer2 interrupt | |
POINTR_PEND | X | ||
Timer3 | POINTR_REQ | 32-bit Timer3 interrupt | |
POINTR_PEND | X | ||
Timer4 | POINTR_REQ | 32-bit Timer4 interrupt | |
POINTR_PEND | X | ||
Timer5 | POINTR_REQ | 32-bit Timer5 interrupt | |
POINTR_PEND | X | ||
Timer6 | POINTR_REQ | 32-bit Timer6 interrupt | |
POINTR_PEND | X | ||
Timer7 | POINTR_REQ | 32-bit Timer7 interrupt | |
POINTR_PEND | X | ||
WDTimer1 | PO_INT_REQ | X | Watchdog Timer |
I2C0 | POINTRREQ | I2C Bus interrupt | |
POINTRPEND | X | ||
I2C1 | POINTRREQ | ||
POINTRPEND | X | ||
SPI | SINTERRUPTN | X | SPI Interrupt |
SDIO | IRQOQN | X | SDIO interrupt |
McASP 0 | MCASP_X_INTR_REQ | McASP 0 Transmit interrupt | |
MCASP_X_INTR_PEND | X | ||
MCASP_R_INTR_REQ | McASP 0 Receive interrupt | ||
MCASP_R_INTR_PEND | X | ||
McASP 1 | MCASP_X_INTR_REQ | McASP 1 Transmit interrupt | |
MCASP_X_INTR_PEND | X | ||
MCASP_R_INTR_REQ | McASP 1 Receive interrupt | ||
MCASP_R_INTR_PEND | X | ||
McASP 2 | MCASP_X_INTR_REQ | McASP 2 Transmit interrupt | |
MCASP_X_INTR_PEND | X | ||
MCASP_R_INTR_REQ | McASP 2 Receive interrupt | ||
MCASP_R_INTR_PEND | X | ||
McBSP | PORRINTERRUPT | McBSP Receive Int (legacy mode) | |
PORXINTERRUPT | McBSP Transmit Int (legacy mode) | ||
PORROVFLINTERRUPT | McBSP Receive Overflow Int (legacy mode) | ||
PORCOMMONIRQ | X | McBSP Common Int | |
RTC | TIMER_INTR_REQ | Timer interrupt | |
TIMER_INTR_PEND | X | ||
ALARM_INTR_REQ | Alarm interrupt | ||
ALARM_INTR_PEND | X | ||
GPIO 0 | POINTRREQ1 | GPIO 0 interrupt 1 | |
POINTRPEND1 | X | ||
POINTRREQ2 | GPIO 0 interrupt 2 | ||
POINTRPEND2 | X | ||
GPIO 1 | POINTRREQ1 | GPIO 1 interrupt 1 | |
POINTRPEND1 | X | ||
POINTRREQ2 | GPIO 1 interrupt 2 | ||
POINTRPEND2 | X | ||
PRCM | Reserved | ||
HDVPSS | INTR0_INTR | Intr0 pulse version | |
INTR0_INTR_PEND_N | X | Intr0 level version | |
INTR1_INTR | Intr1 pulse version | ||
INTR1_INTR_PEND_N | Intr1 level version | ||
INTR2_INTR | Intr2 pulse version | ||
INTR2_INTR_PEND_N | Intr2 level version | ||
INTR3_INTR | Intr3 pulse version | ||
INTR3_INTR_PEND_N | Intr3 level version | ||
SGX530 (AM3894 only) |
THALIAIRQ | X | Error in the IMG bus |
TARGETSINTERRUPT | Target slave error interrupt | ||
INITMINTERRUPT | Initiator master error interrupt | ||
HDMI 1.3 Transmit | INTR0_INTR | Intr0 pulse version | |
INTR0_INTR_PEND_N | X | Intr0 level version | |
SmartReflex0 | INTRREQ | SVT SmartReflex interrupt pulse version | |
INTRPEND | X | SVT SmartReflex interrupt level version | |
SmartReflex1 | INTRREQ | HVT SmartReflex interrupt pulse version | |
INTRPEND | X | HVT SmartReflex interrupt level version | |
PBIST | Reserved | ||
Mailbox | MAIL_U0_IRQ | X | Mailbox interrupt |
MAIL_U1_IRQ | |||
MAIL_U2_IRQ | |||
MAIL_U3_IRQ | |||
NMI | NMI_INT | X | NMI Interrupt |
Infrastructure | L3_DBG_IRQ | X | L3 debug error |
L3_APP_IRQ | X | L3 application error | |
DMM | DMM_HIGH_INTRPEND | X | PAT fault |
Cortex™-A8 SS | COMMTX | X | ARM ICECrusher interrupt |
COMMRX | X | ||
BENCH | X | ARM NPMUIRQ | |
ELM_IRQ | X | Error Location process completion | |
EMUINT | X | E2ICE interrupt |
The Cortex™-A8 Interrupt Controller (AINTC) takes ARM device interrupts and maps them to either the interrupt request (IRQ) or fast interrupt request (FIQ) of the ARM with an individual priority level. The AINTC interrupts must be active low-level interrupts.
The AINTC is responsible for prioritizing all service requests from the system peripherals directed to the Cortex™-A8 SS and generating either nIRQ or nFIQ to the host. The type of the interrupt (nIRQ or nFIQ) and the priority of the interrupt inputs are programmable. It has the capability to handle up to 128 requests which can be steered or prioritized as nFIQ or nIRQ interrupt requests.
The general features of the AINTC are:
INTERRUPT NUMBER | ACRONYM | SOURCE |
---|---|---|
0 | EMUINT | Internal |
1 | COMMTX | Internal |
2 | COMMRX | Internal |
3 | BENCH | Internal |
4 | ELM_IRQ | ELM |
5-6 | - | |
7 | NMI | External Pin |
8 | - | |
9 | L3DEBUG | L3 |
10 | L3APPINT | L3 |
11 | - | |
12 | EDMACOMPINT | TPCC |
13 | EDMAMPERR | TPCC |
14 | EDMAERRINT | TPCC |
15 | - | |
16 | SATAINT | SATA |
17 | USBSSINT | USBSS |
18 | USBINT0 | USBSS |
19 | USBINT1 | USBSS |
20-33 | - | |
34 | USBWAKEUP | USBSS |
35 | PCIeWAKEUP | PCIe |
36 | DSSINT | HDVPSS |
37 | GFXINT | SGX530
(AM3894 only) |
38 | HDMIINT | HDMI |
39 | - | |
40 | MACRXTHR0 | EMAC0 |
41 | MACRXINT0 | EMAC0 |
42 | MACTXINT0 | EMAC0 |
43 | MACMISC0 | EMAC0 |
44 | MACRXTHR1 | EMAC1 |
45 | MACRXINT1 | EMAC1 |
46 | MACTXINT1 | EMAC1 |
47 | MACMISC1 | EMAC1 |
48 | PCIINT0 | PCIe |
49 | PCIINT1 | PCIe |
50 | PCIINT2 | PCIe |
51 | PCIINT3 | PCIe |
52-63 | - | |
64 | SDINT | SD, SDIO |
65 | SPIINT | SPI |
66 | - | |
67 | TINT1 | Timer1 |
68 | TINT2 | Timer2 |
69 | TINT3 | Timer3 |
70 | I2CINT0 | I2C0 |
71 | I2CINT1 | I2C1 |
72 | UARTINT0 | UART0 |
73 | UARTINT1 | UART1 |
74 | UARTINT2 | UART2 |
75 | RTCINT | RTC |
76 | RTCALARMINT | RTC |
77 | MBINT | Mailbox |
78-79 | - | |
80 | MCATXINT0 | McASP0 |
81 | MCARXINT0 | McASP0 |
82 | MCATXINT1 | McASP1 |
83 | MCARXINT1 | McASP1 |
84 | MCATXINT2 | McASP2 |
85 | MCARXINT2 | McASP2 |
86 | MCBSPINT | McBSP |
87-90 | - | |
91 | WDTINT | WDTIMER1 |
92 | TINT4 | Timer4 |
93 | TINT5 | Timer5 |
94 | TINT6 | Timer6 |
95 | TINT7 | Timer7 |
96 | GPIOINT0A | GPIO 0 |
97 | GPIOINT0B | GPIO 0 |
98 | GPIOINT1A | GPIO 1 |
99 | GPIOINT1B | GPIO 1 |
100 | GPMCINT | GPMC |
101 | DDRERR0 | DDR EMIF0 |
102 | DDRERR1 | DDR EMIF1 |
103-111 | - | |
112 | TCERRINT0 | TPTC0 |
113 | TCERRINT1 | TPTC1 |
114 | TCERRINT2 | TPTC2 |
115 | TCERRINT3 | TPTC3 |
116-119 | - | |
120 | SMRFLX0 | SmartReflex0 |
121 | SMRFLX1 | SmartReflex1 |
123 | - | |
124 | DMMINT | DMM |
125-127 | - |