SPRS961F August   2016  – November 2019 AM5706 , AM5708

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  CSI2
      5. 4.3.5  EMIF
      6. 4.3.6  GPMC
      7. 4.3.7  Timers
      8. 4.3.8  I2C
      9. 4.3.9  HDQ1W
      10. 4.3.10 UART
      11. 4.3.11 McSPI
      12. 4.3.12 QSPI
      13. 4.3.13 McASP
      14. 4.3.14 USB
      15. 4.3.15 PCIe
      16. 4.3.16 DCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 MLB
      19. 4.3.19 eMMC/SD/SDIO
      20. 4.3.20 GPIO
      21. 4.3.21 KBD
      22. 4.3.22 PWM
      23. 4.3.23 PRU-ICSS
      24. 4.3.24 Emulation and Debug Subsystem
      25. 4.3.25 System and Miscellaneous
        1. 4.3.25.1 Sysboot
        2. 4.3.25.2 Power, Reset, and Clock Management (PRCM)
        3. 4.3.25.3 System Direct Memory Access (SDMA)
        4. 4.3.25.4 Interrupt Controllers (INTC)
      26. 4.3.26 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power on Hours (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
        1. Table 5-4 Voltage Domains Operating Performance Points
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-7  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-8  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-9  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-10 IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-11 LVCMOS CSI2 DC Electrical Characteristics
      6. Table 5-12 BMLB18 Buffers DC Electrical Characteristics
      7. Table 5-13 Dual Voltage SDIO1833 DC Electrical Characteristics
      8. Table 5-14 Dual Voltage LVCMOS DC Electrical Characteristics
      9. 5.7.1      USBPHY DC Electrical Characteristics
      10. 5.7.2      HDMIPHY DC Electrical Characteristics
      11. 5.7.3      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-15 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Resistance Characteristics for CBD Package
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8 V and 3.3 V Signal Transition Levels
          2. 5.10.1.1.2 1.8 V and 3.3 V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
          4. 5.10.4.1.4 RC On-die Oscillator Clock
        2. 5.10.4.2 Output Clocks
        3. 5.10.4.3 DPLLs, DLLs
          1. 5.10.4.3.1 DPLL Characteristics
          2. 5.10.4.3.2 DLL Characteristics
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  CSI2
          1. 5.10.6.6.1 CSI-2 MIPI D-PHY
        7. 5.10.6.7  EMIF
        8. 5.10.6.8  GPMC
          1. 5.10.6.8.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.8.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.8.3 GPMC/NAND Flash Interface Asynchronous Timing
        9. 5.10.6.9  Timers
        10. 5.10.6.10 I2C
          1. Table 5-57 Timing Requirements for I2C Input Timings
          2. Table 5-58 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
          3. Table 5-59 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        11. 5.10.6.11 HDQ1W
          1. 5.10.6.11.1 HDQ / 1-Wire — HDQ Mode
          2. 5.10.6.11.2 HDQ/1-Wire—1-Wire Mode
        12. 5.10.6.12 UART
          1. Table 5-64 Timing Requirements for UART
          2. Table 5-65 Switching Characteristics Over Recommended Operating Conditions for UART
        13. 5.10.6.13 McSPI
        14. 5.10.6.14 QSPI
        15. 5.10.6.15 McASP
          1. Table 5-72 Timing Requirements for McASP1
          2. Table 5-73 Timing Requirements for McASP2
          3. Table 5-74 Timing Requirements for McASP3/4/5/6/7/8
        16. 5.10.6.16 USB
          1. 5.10.6.16.1 USB1 DRD PHY
          2. 5.10.6.16.2 USB2 PHY
        17. 5.10.6.17 PCIe
        18. 5.10.6.18 DCAN
          1. Table 5-89 Timing Requirements for DCANx Receive
          2. Table 5-90 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
        19. 5.10.6.19 GMAC_SW
          1. 5.10.6.19.1 GMAC MII Timings
            1. Table 5-91 Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-92 Timing Requirements for miin_txclk - MII Operation
            3. Table 5-93 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-94 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.19.2 GMAC MDIO Interface Timings
          3. 5.10.6.19.3 GMAC RMII Timings
            1. Table 5-99  Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-100 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-101 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-102 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.19.4 GMAC RGMII Timings
            1. Table 5-106 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-107 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-108 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-109 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        20. 5.10.6.20 eMMC/SD/SDIO
          1. 5.10.6.20.1 MMC1—SD Card Interface
            1. 5.10.6.20.1.1 Default speed, 4-bit data, SDR, half-cycle
            2. 5.10.6.20.1.2 High speed, 4-bit data, SDR, half-cycle
            3. 5.10.6.20.1.3 SDR12, 4-bit data, half-cycle
            4. 5.10.6.20.1.4 SDR25, 4-bit data, half-cycle
            5. 5.10.6.20.1.5 UHS-I SDR50, 4-bit data, half-cycle
            6. 5.10.6.20.1.6 UHS-I SDR104, 4-bit data, half-cycle
            7. 5.10.6.20.1.7 UHS-I DDR50, 4-bit data
          2. 5.10.6.20.2 MMC2 — eMMC
            1. 5.10.6.20.2.1 Standard JC64 SDR, 8-bit data, half cycle
            2. 5.10.6.20.2.2 High-speed JC64 SDR, 8-bit data, half cycle
            3. 5.10.6.20.2.3 High-speed HS200 JEDS84 SDR, 8-bit data, half cycle
            4. 5.10.6.20.2.4 High-speed JC64 DDR, 8-bit data
              1. Table 5-134 Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
          3. 5.10.6.20.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.20.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.20.3.2 MMC3 and MMC4, SD High Speed
            3. 5.10.6.20.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.20.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.20.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
        21. 5.10.6.21 GPIO
        22. 5.10.6.22 PRU-ICSS
          1. 5.10.6.22.1 Programmable Real-Time Unit (PRU-ICSS PRU)
            1. 5.10.6.22.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
              1. Table 5-156 PRU-ICSS PRU Timing Requirements - Direct Input Mode
              2. Table 5-157 PRU-ICSS PRU Switching Requirements – Direct Output Mode
            2. 5.10.6.22.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
              1. Table 5-158 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            3. 5.10.6.22.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
              1. Table 5-159 PRU-ICSS PRU Timing Requirements – Shift In Mode
              2. Table 5-160 PRU-ICSS PRU Switching Requirements - Shift Out Mode
            4. 5.10.6.22.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
              1. Table 5-161 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
              2. Table 5-162 PRU-ICSS PRU Timing Requirements - EnDAT Mode
              3. Table 5-163 PRU-ICSS PRU Switching Requirements - EnDAT Mode
          2. 5.10.6.22.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
            1. 5.10.6.22.2.1 PRU-ICSS ECAT Electrical Data and Timing
              1. Table 5-164 PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
              2. Table 5-165 PRU-ICSS ECAT Timing Requirements – Input Validated With SYNCx
              3. Table 5-166 PRU-ICSS ECAT Timing Requirements – Input Validated With Start of Frame (SOF)
              4. Table 5-167 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
              5. Table 5-168 PRU-ICSS ECAT Switching Requirements - Digital IOs
          3. 5.10.6.22.3 PRU-ICSS MII_RT and Switch
            1. 5.10.6.22.3.1 PRU-ICSS MDIO Electrical Data and Timing
              1. Table 5-169 PRU-ICSS MDIO Timing Requirements – MDIO_DATA
              2. Table 5-170 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
              3. Table 5-171 PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
            2. 5.10.6.22.3.2 PRU-ICSS MII_RT Electrical Data and Timing
              1. Table 5-172 PRU-ICSS MII_RT Timing Requirements – MII[x]_RXCLK
              2. Table 5-173 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
              3. Table 5-174 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
              4. Table 5-175 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
          4. 5.10.6.22.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. Table 5-176 Timing Requirements for PRU-ICSS UART Receive
            2. Table 5-177 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
          5. 5.10.6.22.5 PRU-ICSS IOSETs
          6. 5.10.6.22.6 PRU-ICSS Manual Functional Mapping
        23. 5.10.6.23 System and Miscellaneous interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-194 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-195 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-196 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-197 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 Trace Port Interface Unit (TPIU)
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  MPU
    4. 6.4  DSP Subsystem
    5. 6.5  PRU-ICSS
    6. 6.6  Memory Subsystem
      1. 6.6.1 EMIF
      2. 6.6.2 GPMC
      3. 6.6.3 ELM
      4. 6.6.4 OCMC
    7. 6.7  Interprocessor Communication
      1. 6.7.1 MailBox
      2. 6.7.2 Spinlock
    8. 6.8  Interrupt Controller
    9. 6.9  EDMA
    10. 6.10 Peripherals
      1. 6.10.1  VIP
      2. 6.10.2  DSS
      3. 6.10.3  Timers
        1. 6.10.3.1 General-Purpose Timers
        2. 6.10.3.2 32-kHz Synchronized Timer (COUNTER_32K)
        3. 6.10.3.3 Watchdog Timer
      4. 6.10.4  I2C
      5. 6.10.5  UART
        1. 6.10.5.1 UART Features
        2. 6.10.5.2 IrDA Features
        3. 6.10.5.3 CIR Features
      6. 6.10.6  McSPI
      7. 6.10.7  QSPI
      8. 6.10.8  McASP
      9. 6.10.9  USB
      10. 6.10.10 PCIe
      11. 6.10.11 DCAN
      12. 6.10.12 GMAC_SW
      13. 6.10.13 eMMC/SD/SDIO
      14. 6.10.14 GPIO
      15. 6.10.15 ePWM
      16. 6.10.16 eCAP
      17. 6.10.17 eQEP
    11. 6.11 On-chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Power Supply Mapping
    2. 7.2 DDR3 Board Design and Layout Guidelines
      1. 7.2.1 DDR3 General Board Layout Guidelines
      2. 7.2.2 DDR3 Board Design and Layout Guidelines
        1. 7.2.2.1  Board Designs
        2. 7.2.2.2  DDR3 EMIF
        3. 7.2.2.3  DDR3 Device Combinations
        4. 7.2.2.4  DDR3 Interface Schematic
          1. 7.2.2.4.1 32-Bit DDR3 Interface
          2. 7.2.2.4.2 16-Bit DDR3 Interface
        5. 7.2.2.5  Compatible JEDEC DDR3 Devices
        6. 7.2.2.6  PCB Stackup
        7. 7.2.2.7  Placement
        8. 7.2.2.8  DDR3 Keepout Region
        9. 7.2.2.9  Bulk Bypass Capacitors
        10. 7.2.2.10 High-Speed Bypass Capacitors
          1. 7.2.2.10.1 Return Current Bypass Capacitors
        11. 7.2.2.11 Net Classes
        12. 7.2.2.12 DDR3 Signal Termination
        13. 7.2.2.13 VREF_DDR Routing
        14. 7.2.2.14 VTT
        15. 7.2.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.2.2.15.1 Four DDR3 Devices
            1. 7.2.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.2.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.2.2.15.2 Two DDR3 Devices
            1. 7.2.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.2.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.2.2.15.3 One DDR3 Device
            1. 7.2.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.2.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.2.2.16 Data Topologies and Routing Definition
          1. 7.2.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.2.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.2.2.17 Routing Specification
          1. 7.2.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.2.2.17.2 DQS and DQ Routing Specification
    3. 7.3 High Speed Differential Signal Routing Guidance
    4. 7.4 Power Distribution Network Implementation Guidance
    5. 7.5 Thermal Solution Guidance
    6. 7.6 Single-Ended Interfaces
      1. 7.6.1 General Routing Guidelines
      2. 7.6.2 QSPI Board Design and Layout Guidelines
    7. 7.7 LJCB_REFN/P Connections
    8. 7.8 Clock Routing Guidelines
      1. 7.8.1 Oscillator Ground Connection
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Related Links
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • CBD|538
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.10.13 eMMC/SD/SDIO

The eMMC/SD/SDIO host controller provides an interface between a local host (LH) such as a microprocessor unit (MPU) or digital signal processor (DSP) and either eMMC, SD® memory cards, or SDIO cards and handles eMMC/SD/SDIO transactions with minimal LH intervention.

Optionally, the controller is connected to the L3_MAIN interconnect to have a direct access to system memory. It also supports two direct memory access (DMA) slave channels or a DMA master access (in this case, slave DMA channels are deactivated) depending on its integration.

The eMMC/SD/SDIO host controller deals with eMMC/SD/SDIO protocol at transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit, and checking for syntactical correctness.

The application interface can send every eMMC/SD/SDIO command and poll for the status of the adapter or wait for an interrupt request, which is sent back in case of exceptions or to warn of end of operation.

The application interface can read card responses or flag registers. It can also mask individual interrupt sources. All these operations can be performed by reading and writing control registers. The eMMC/SD/SDIO host controller also supports two DMA channels.

There are four eMMC/SD/SDIO host controllers inside the device. gives an overview of the eMMC/SD/SDIOi (i = 1 to 4) controllers.

Each controller has the following data width:

  • eMMC/SD/SDIO1 - 4-bit wide data bus
  • eMMC/SD/SDIO2 - 8-bit wide data bus
  • eMMC/SD/SDIO3 - 8-bit wide data bus
  • eMMC/SD/SDIO4 - 4-bit wide data bus

The eMMC/SD/SDIOi controller is also referred to as MMCi.

Compliance with standards:

  • Full compliance with MMC/eMMC command/response sets as defined in the JC64 MMC/eMMC standard specification, v4.5.
  • Full compliance with SD command/response sets as defined in the SD Physical Layer specification v3.01
  • Full compliance with SDIO command/response sets and interrupt/read-wait suspend-resume operations as defined in the SD part E1 specification v3.00
  • Full compliance with SD Host Controller Standard Specification sets as defined in the SD card specification Part A2 v3.00

Main features of the eMMC/SD/SDIO host controllers:

  • Flexible architecture allowing support for new command structure
  • 32-bit wide access bus to maximize bus throughput
  • Designed for low power
  • Programmable clock generation
  • Dedicated DLL to support SDR104 mode (MMC1 only)
  • Dedicated DLL to support HS200 mode (MMC2 only)
  • Card insertion/removal detection and write protect detection
  • L4 slave interface supports:
    • 32-bit data bus width
    • 8/16/32 bit access supported
    • 9-bit address bus width
    • Streaming burst supported only with burst length up to 7
    • WNP supported
  • L3 initiator interface Supports:
    • 32-bit data bus width
    • 8/16/32 bit access supported
    • 32-bit address bus width
    • Burst supported
  • Built-in 1024-byte buffer for read or write
  • Two DMA channels, one interrupt line
  • Support JC 64 v4.4.1 boot mode operations
  • Support SDA 3.00 Part A2 programming model
  • Support SDA 3.00 Part A2 DMA feature (ADMA2)
  • Supported data transfer rates:
    • MMCi supports the following SD v3.0 data transfer rates:
      • DS mode (3.3V IOs): up to 12 MBps (24 MHz clock)
      • HS mode (3.3V IOs): up to 24 MBps (48 MHz clock)
      • SDR12 (1.8V IOs): up to 12 MBps (24 MHz clock)
      • SDR25 (1.8V IOs): up to 24 MBps (48 MHz clock)
      • SDR50 (1.8V IOs): up to 48 MBps (96 MHz clock) - MMC1 and MMC3 only
      • DDR50 (1.8V IOs): up to 48 MBps (48 MHz clock) - MMC1 only
      • SDR104 (1.8V IOs) cards can be supported up to 192 MHz clock (96 MBps max) - MMC1 only
    • MMCi supports the Default SD mode 1-bit data transfer up to 24Mbps (3MBps)
    • Only MMC2 supports also the following JC64 v4.5 data transfer rates:
      • Up to 192 MBps in eMMC mode, 8-bit SDR mode (192 MHz clock frequency)
      • Up to 96 MBps in eMMC mode, 8-bit DDR mode (48 MHz clock frequency)
  • All eMMC/SD/SDIO controllers are connected to 1.8V/3.3V compatible I/Os to support 1.8V/3.3V signaling

NOTE

eMMC functionality is supported fully by MMC2 only. The other MMC modules are capable of eMMC functionality, but are not timing-optimized for eMMC.

The differences between the eMMC/SD/SDIO host controllers and a standard SD host controller defined by the SD Card Specification, Part A2, SD Host Controller Standard Specification, v3.0 are:

  • The clock divider in the eMMC/SD/SDIO host controller supports a wider range of frequency than specified in the SD Memory Card Specifications, v3.0. The eMMC/SD/SDIO host controller supports odd and even clock ratio.
  • The eMMC/SD/SDIO host controller supports configurable busy time-out.
  • ADMA2 64-bit mode is not supported.
  • There is no external LED control.

NOTE

Only even ratios are supported in DDR mode.

For more information, see chapter eMMC/SD/SDIO of the Device TRM.