SPRS961F August 2016 – November 2019 AM5706 , AM5708
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
NOTE
For more information, see the Memory Subsystem / General-Purpose Memory Controller section of the Device TRM.
SIGNAL NAME | DESCRIPTION | TYPE | BALL |
---|---|---|---|
gpmc_ad0 | GPMC Data 0 in A/D nonmultiplexed mode and additionally Address 1 in A/D multiplexed mode | IO | F1 |
gpmc_ad1 | GPMC Data 1 in A/D nonmultiplexed mode and additionally Address 2 in A/D multiplexed mode | IO | E2 |
gpmc_ad2 | GPMC Data 2 in A/D nonmultiplexed mode and additionally Address 3 in A/D multiplexed mode | IO | E1 |
gpmc_ad3 | GPMC Data 3 in A/D nonmultiplexed mode and additionally Address 4 in A/D multiplexed mode | IO | C1 |
gpmc_ad4 | GPMC Data 4 in A/D nonmultiplexed mode and additionally Address 5 in A/D multiplexed mode | IO | D1 |
gpmc_ad5 | GPMC Data 5 in A/D nonmultiplexed mode and additionally Address 6 in A/D multiplexed mode | IO | D2 |
gpmc_ad6 | GPMC Data 6 in A/D nonmultiplexed mode and additionally Address 7 in A/D multiplexed mode | IO | B1 |
gpmc_ad7 | GPMC Data 7 in A/D nonmultiplexed mode and additionally Address 8 in A/D multiplexed mode | IO | B2 |
gpmc_ad8 | GPMC Data 8 in A/D nonmultiplexed mode and additionally Address 9 in A/D multiplexed mode | IO | C2 |
gpmc_ad9 | GPMC Data 9 in A/D nonmultiplexed mode and additionally Address 10 in A/D multiplexed mode | IO | D3 |
gpmc_ad10 | GPMC Data 10 in A/D nonmultiplexed mode and additionally Address 11 in A/D multiplexed mode | IO | A2 |
gpmc_ad11 | GPMC Data 11 in A/D nonmultiplexed mode and additionally Address 12 in A/D multiplexed mode | IO | B3 |
gpmc_ad12 | GPMC Data 12 in A/D nonmultiplexed mode and additionally Address 13 in A/D multiplexed mode | IO | C3 |
gpmc_ad13 | GPMC Data 13 in A/D nonmultiplexed mode and additionally Address 14 in A/D multiplexed mode | IO | C4 |
gpmc_ad14 | GPMC Data 14 in A/D nonmultiplexed mode and additionally Address 15 in A/D multiplexed mode | IO | A3 |
gpmc_ad15 | GPMC Data 15 in A/D nonmultiplexed mode and additionally Address 16 in A/D multiplexed mode | IO | B4 |
gpmc_a0 | GPMC Address 0. Only used to effectively address 8-bit data nonmultiplexed memories | O | G1, M1 |
gpmc_a1 | GPMC address 1 in A/D nonmultiplexed mode and Address 17 in A/D multiplexed mode | O | G3, M2 |
gpmc_a2 | GPMC address 2 in A/D nonmultiplexed mode and Address 18 in A/D multiplexed mode | O | H5, L2 |
gpmc_a3 | GPMC address 3 in A/D nonmultiplexed mode and Address 19 in A/D multiplexed mode | O | H6, L1 |
gpmc_a4 | GPMC address 4 in A/D nonmultiplexed mode and Address 20 in A/D multiplexed mode | O | K3 |
gpmc_a5 | GPMC address 5 in A/D nonmultiplexed mode and Address 21 in A/D multiplexed mode | O | K2 |
gpmc_a6 | GPMC address 6 in A/D nonmultiplexed mode and Address 22 in A/D multiplexed mode | O | J1 |
gpmc_a7 | GPMC address 7 in A/D nonmultiplexed mode and Address 23 in A/D multiplexed mode | O | K1 |
gpmc_a8 | GPMC address 8 in A/D nonmultiplexed mode and Address 24 in A/D multiplexed mode | O | K4 |
gpmc_a9 | GPMC address 9 in A/D nonmultiplexed mode and Address 25 in A/D multiplexed mode | O | H1 |
gpmc_a10 | GPMC address 10 in A/D nonmultiplexed mode and Address 26 in A/D multiplexed mode | O | J2 |
gpmc_a11 | GPMC address 11 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | L3 |
gpmc_a12 | GPMC address 12 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | G1 |
gpmc_a13 | GPMC address 13 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | A4, H3, G4 |
gpmc_a14 | GPMC address 14 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | E7, H4, G3 |
gpmc_a15 | GPMC address 15 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | D6, K6, F6 |
gpmc_a16 | GPMC address 16 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | C5, K5, M1 |
gpmc_a17 | GPMC address 17 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | B5, G2, D8 |
gpmc_a18 | GPMC address 18 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | D7, F2, C7 |
gpmc_a19 | GPMC address 19 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | A4(3), C6, H5 |
gpmc_a20 | GPMC address 20 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | A5, E7(3), L4 |
gpmc_a21 | GPMC address 21 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | B6, D6(3), H2 |
gpmc_a22 | GPMC address 22 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | A6, C5(3), H6 |
gpmc_a23 | GPMC address 23 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | B5, H5, C10, G4 |
gpmc_a24 | GPMC address 24 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | D7(3), D10, G3 |
gpmc_a25 | GPMC address 25 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | C6(3), F6, E10 |
gpmc_a26 | GPMC address 26 in A/D nonmultiplexed mode and unused in A/D multiplexed mode | O | A5(3), M1, B10 |
gpmc_a27 | GPMC address 27 in A/D nonmultiplexed mode and Address 27 in A/D multiplexed mode | O | B6(3), D8, C7, E8 |
gpmc_cs0 | GPMC Chip Select 0 (active low) | O | F3 |
gpmc_cs1 | GPMC Chip Select 1 (active low) | O | A6 |
gpmc_cs2 | GPMC Chip Select 2 (active low) | O | G4 |
gpmc_cs3 | GPMC Chip Select 3 (active low) | O | G3 |
gpmc_cs4 | GPMC Chip Select 4 (active low) | O | H2 |
gpmc_cs5 | GPMC Chip Select 5 (active low) | O | H6 |
gpmc_cs6 | GPMC Chip Select 6 (active low) | O | H5 |
gpmc_cs7 | GPMC Chip Select 7 (active low) | O | L4 |
gpmc_clk(1)(2) | GPMC Clock output | IO | L4 |
gpmc_advn_ale | GPMC address valid active low or address latch enable | O | H5 |
gpmc_oen_ren | GPMC output enable active low or read enable | O | G5 |
gpmc_wen | GPMC write enable active low | O | G6 |
gpmc_ben0 | GPMC lower-byte enable active low | O | H2 |
gpmc_ben1 | GPMC upper-byte enable active low | O | H6 |
gpmc_wait0 | GPMC external indication of wait 0 | I | F6 |
gpmc_wait1 | GPMC external indication of wait 1 | I | H5, L4 |