SPRS961F August 2016 – November 2019 AM5706 , AM5708
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Table 5-133 and Table 5-134 present Timing requirements and Switching characteristics for MMC2 - High speed DDR in receiver and transmitter mode (see Figure 5-92 and Figure 5-93).
NO. | PARAMETER | DESCRIPTION | MODE | MIN | MAX | UNIT |
---|---|---|---|---|---|---|
DDR3 | tsu(cmdV-clk) | Setup time, mmc2_cmd valid before mmc2_clk transition | 1.8 | ns | ||
DDR4 | th(clk-cmdV) | Hold time, mmc2_cmd valid after mmc2_clk transition | 1.6 | ns | ||
DDR7 | tsu(dV-clk) | Setup time, mmc2_dat[7:0] valid before mmc2_clk transition | 1.8 | ns | ||
DDR8 | th(clk-dV) | Hold time, mmc2_dat[7:0] valid after mmc2_clk transition | Pad Loopback (1.8V and 3.3V), Boot | 1.6 | ns | |
Internal Loopback (1.8V with MMC2_VIRTUAL2) | 1.86 | ns | ||||
Internal Loopback (3.3V with MMC2_VIRTUAL2) | 1.95 | ns | ||||
Internal Loopback (1.8V with MMC2_MANUAL2) | ns | |||||
Internal Loopback (3.3V with MMC2_MANUAL2) | 1.6 | ns |