SPRS961F August 2016 – November 2019 AM5706 , AM5708
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
PARAMETER | MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|---|
Signal Names in MUXMODE 0 (Single-Ended Signals): ddr1_d[31:0], ddr1_a[15:0], ddr1_dqm[3:0], ddr1_ba[2:0], ddr1_csn0, ddr1_cke, ddr1_odt0, ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_rst | ||||||
Balls:AA23 / AC24 / AB24 / AD24 / AB23 / AC23 / AD23 / AE24 / AA24 / W25 / Y23 / AD25 / AC25 / AB25 / AA25 / W24 / W23 / U25 / U24 / W21 / T22 / U22 / U23 / T21 / T23 / T25 / T24 / P21 / N21 / P22 / P23 / P24 / AC18 / AE19 / AD19 / AB19 / AD20 / AE20 / AA18 / AA20 / Y21 / AC20 / AA21 / AC21 / AC22 / AC15 / AB15 / AC16 / AE23 / W22 / U21 / P25 / AE16 / AA16 / AB16 / AC19 / AB18 / AD18 / AD16 / AD17 / AE18 / AE17 | ||||||
Driver Mode | ||||||
VOH | High-level output threshold (IOH = 0.1 mA) | 0.9 × VDDS | V | |||
VOL | Low-level output threshold (IOL = 0.1 mA) | 0.1 × VDDS | V | |||
CPAD | Pad capacitance (including package capacitance) | 3 | pF | |||
ZO | Output impedance (drive strength) | l[2:0] = 000 (Imp80) | 80 | Ω | ||
l[2:0] = 001 (Imp60) | 60 | |||||
l[2:0] = 010 (Imp48) | 48 | |||||
l[2:0] = 011 (Imp40) | 40 | |||||
l[2:0] = 100 (Imp34) | 34 | |||||
Single-Ended Receiver Mode | ||||||
VIH | High-level input threshold | DDR3/DDR3L | VREF+0.1 | VDDS+0.2 | V | |
VIL | Low-level input threshold | DDR3/DDR3L | -0.2 | VREF-0.1 | V | |
VCM | Input common-mode voltage | VREF -10%vdds | VREF+ 10%vdds | V | ||
CPAD | Pad capacitance (including package capacitance) | 3 | pF | |||
Signal Names in MUXMODE 0 (Differential Signals): ddr1_ck, ddr1_nck, ddr1_dqs[3:0], ddr1_dqsn[3:0] | ||||||
Bottom Balls:AD21 / AE21 / AD22 / AE22 / Y24 / Y25 / V24 / V25 / R24 / R25 | ||||||
Driver Mode | ||||||
VOH | High-level output threshold (IOH = 0.1 mA) | 0.9 × VDDS | V | |||
VOL | Low-level output threshold (IOL = 0.1 mA) | 0.1 × VDDS | V | |||
CPAD | Pad capacitance (including package capacitance) | 3 | pF | |||
ZO | Output impedance (drive strength) | l[2:0] = 000 (Imp80) | 80 | Ω | ||
l[2:0] = 001 (Imp60) | 60 | |||||
l[2:0] = 010 (Imp48) | 48 | |||||
l[2:0] = 011 (Imp40) | 40 | |||||
l[2:0] = 100 (Imp34) | 34 | |||||
Single-Ended Receiver Mode | ||||||
VIH | High-level input threshold | DDR3/DDR3L | VREF+0.1 | VDDS+0.2 | V | |
VIL | Low-level input threshold | DDR3/DDR3L | -0.2 | VREF-0.1 | V | |
VCM | Input common-mode voltage | VREF -10%vdds | VREF+ 10%vdds | V | ||
CPAD | Pad capacitance (including package capacitance) | 3 | pF | |||
Differential Receiver Mode | ||||||
VSWING | Input voltage swing | DDR3/DDR3L | 0.2 | vdds+0.4 | V | |
VCM | Input common-mode voltage | VREF -10%vdds | VREF+ 10%vdds | V | ||
CPAD | Pad capacitance (including package capacitance) | 3 | pF |