SPRS961F August 2016 – November 2019 AM5706 , AM5708
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Table 5-121 and Table 5-122 present Timing requirements and Switching characteristics for MMC1 - SDR50 in receiver and transmitter mode (see Figure 5-81 and Figure 5-82).
NO. | PARAMETER | DESCRIPTION | MODE | MIN | MAX | UNIT |
---|---|---|---|---|---|---|
SDR503 | tsu(cmdV-clkH) | Setup time, mmc1_cmd valid before mmc1_clk rising clock edge | 1.48 | ns | ||
SDR504 | th(clkH-cmdV) | Hold time, mmc1_cmd valid after mmc1_clk rising clock edge | 1.7 | ns | ||
SDR507 | tsu(dV-clkH) | Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge | 1.48 | ns | ||
SDR508 | th(clkH-dV) | Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge | Pad Loopback Clock | 1.7 | ns | |
Internal Loopback Clock | 1.6 | ns |
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
SDR501 | fop(clk) | Operating frequency, mmc1_clk | 96 | MHz | |
SDR502H | tw(clkH) | Pulse duration, mmc1_clk high | 0.5 × P-0.185 (1) | ns | |
SDR502L | tw(clkL) | Pulse duration, mmc1_clk low | 0.5 × P-0.185 (1) | ns | |
SDR505 | td(clkL-cmdV) | Delay time, mmc1_clk falling clock edge to mmc1_cmd transition | -8.8 | 6.6 | ns |
SDR506 | td(clkL-dV) | Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition | -3.66 | 1.46 | ns |