SPRS957I March   2016  – November 2019 AM5716 , AM5718

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Terminal Assignment
      1. 4.1.1 Unused Balls Connection Requirements
    2. 4.2 Ball Characteristics
    3. 4.3 Multiplexing Characteristics
    4. 4.4 Signal Descriptions
      1. 4.4.1  Video Input Ports (VIP)
      2. 4.4.2  Display Subsystem – Video Output Ports
      3. 4.4.3  Display Subsystem – High-Definition Multimedia Interface (HDMI)
      4. 4.4.4  Camera Serial Interface 2 CAL bridge (CSI2)
      5. 4.4.5  External Memory Interface (EMIF)
      6. 4.4.6  General-Purpose Memory Controller (GPMC)
      7. 4.4.7  Timers
      8. 4.4.8  Inter-Integrated Circuit Interface (I2C)
      9. 4.4.9  HDQ / 1-Wire Interface (HDQ1W)
      10. 4.4.10 Universal Asynchronous Receiver Transmitter (UART)
      11. 4.4.11 Multichannel Serial Peripheral Interface (McSPI)
      12. 4.4.12 Quad Serial Peripheral Interface (QSPI)
      13. 4.4.13 Multichannel Audio Serial Port (McASP)
      14. 4.4.14 Universal Serial Bus (USB)
      15. 4.4.15 SATA
      16. 4.4.16 Peripheral Component Interconnect Express (PCIe)
      17. 4.4.17 Controller Area Network Interface (DCAN)
      18. 4.4.18 Ethernet Interface (GMAC_SW)
      19. 4.4.19 Media Local Bus (MLB) Interface
      20. 4.4.20 eMMC/SD/SDIO
      21. 4.4.21 General-Purpose Interface (GPIO)
      22. 4.4.22 Keyboard controller (KBD)
      23. 4.4.23 Pulse Width Modulation (PWM) Interface
      24. 4.4.24 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
      25. 4.4.25 Test Interfaces
      26. 4.4.26 System and Miscellaneous
        1. 4.4.26.1 Sysboot
        2. 4.4.26.2 Power, Reset, and Clock Management (PRCM)
        3. 4.4.26.3 Real-Time Clock (RTC) Interface
        4. 4.4.26.4 System Direct Memory Access (SDMA)
        5. 4.4.26.5 Interrupt Controllers (INTC)
        6. 4.4.26.6 Observability
      27. 4.4.27 Power Supplies
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On-Hour (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. 5.7.1  LVCMOS DDR DC Electrical Characteristics
      2. 5.7.2  HDMIPHY DC Electrical Characteristics
      3. 5.7.3  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      4. 5.7.4  IQ1833 Buffers DC Electrical Characteristics
      5. 5.7.5  IHHV1833 Buffers DC Electrical Characteristics
      6. 5.7.6  LVCMOS OSC Buffers DC Electrical Characteristics
      7. 5.7.7  LVCMOS CSI2 DC Electrical Characteristics
      8. 5.7.8  BMLB18 Buffers DC Electrical Characteristics
      9. 5.7.9  BC1833IHHV Buffers DC Electrical Characteristics
      10. 5.7.10 USBPHY DC Electrical Characteristics
      11. 5.7.11 Dual Voltage SDIO1833 DC Electrical Characteristics
      12. 5.7.12 Dual Voltage LVCMOS DC Electrical Characteristics
      13. 5.7.13 SATAPHY DC Electrical Characteristics
      14. 5.7.14 SERDES DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-21 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Characteristics
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Power Supply Sequences
  6. 6 Clock Specifications
    1. 6.1 Input Clock Specifications
      1. 6.1.1 Input Clock Requirements
      2. 6.1.2 System Oscillator OSC0 Input Clock
        1. 6.1.2.1 OSC0 External Crystal
        2. 6.1.2.2 OSC0 Input Clock
      3. 6.1.3 Auxiliary Oscillator OSC1 Input Clock
        1. 6.1.3.1 OSC1 External Crystal
        2. 6.1.3.2 OSC1 Input Clock
      4. 6.1.4 RTC Oscillator Input Clock
        1. 6.1.4.1 RTC Oscillator External Crystal
        2. 6.1.4.2 RTC Oscillator Input Clock
        3. 6.1.4.3 RC On-die Oscillator Clock
    2. 6.2 DPLLs, DLLs Specifications
      1. 6.2.1 DPLL Characteristics
      2. 6.2.2 DLL Characteristics
  7. 7 Timing Requirements and Switching Characteristics
    1. 7.1  Timing Test Conditions
    2. 7.2  Interface Clock Specifications
      1. 7.2.1 Interface Clock Terminology
      2. 7.2.2 Interface Clock Frequency
    3. 7.3  Timing Parameters and Information
      1. 7.3.1 Parameter Information
        1. 7.3.1.1 1.8V and 3.3V Signal Transition Levels
        2. 7.3.1.2 1.8V and 3.3V Signal Transition Rates
        3. 7.3.1.3 Timing Parameters and Board Routing Analysis
    4. 7.4  Recommended Clock and Control Signal Transition Behavior
    5. 7.5  Virtual and Manual I/O Timing Modes
    6. 7.6  Video Input Ports (VIP)
    7. 7.7  Display Subsystem - Video Output Ports
    8. 7.8  Display Subsystem - High-Definition Multimedia Interface (HDMI)
    9. 7.9  Camera Serial Interface 2 CAL bridge (CSI2)
      1. 7.9.1 CSI-2 MIPI D-PHY
    10. 7.10 External Memory Interface (EMIF)
    11. 7.11 General-Purpose Memory Controller (GPMC)
      1. 7.11.1 GPMC/NOR Flash Interface Synchronous Timing
      2. 7.11.2 GPMC/NOR Flash Interface Asynchronous Timing
      3. 7.11.3 GPMC/NAND Flash Interface Asynchronous Timing
    12. 7.12 Timers
    13. 7.13 Inter-Integrated Circuit Interface (I2C)
      1. Table 7-33 Timing Requirements for I2C Input Timings
      2. Table 7-34 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
      3. Table 7-35 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
    14. 7.14 HDQ / 1-Wire Interface (HDQ1W)
      1. 7.14.1 HDQ / 1-Wire - HDQ Mode
      2. 7.14.2 HDQ/1-Wire-1-Wire Mode
    15. 7.15 Universal Asynchronous Receiver Transmitter (UART)
      1. Table 7-40 Timing Requirements for UART
      2. Table 7-41 Switching Characteristics Over Recommended Operating Conditions for UART
    16. 7.16 Multichannel Serial Peripheral Interface (McSPI)
    17. 7.17 Quad Serial Peripheral Interface (QSPI)
    18. 7.18 Multichannel Audio Serial Port (McASP)
      1. Table 7-48 Timing Requirements for McASP1
      2. Table 7-49 Timing Requirements for McASP2
      3. Table 7-50 Timing Requirements for McASP3/4/5/6/7/8
    19. 7.19 Universal Serial Bus (USB)
      1. 7.19.1 USB1 DRD PHY
      2. 7.19.2 USB2 PHY
    20. 7.20 Serial Advanced Technology Attachment (SATA)
    21. 7.21 Peripheral Component Interconnect Express (PCIe)
    22. 7.22 Controller Area Network Interface (DCAN)
      1. Table 7-65 Timing Requirements for DCANx Receive
      2. Table 7-66 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
    23. 7.23 Ethernet Interface (GMAC_SW)
      1. 7.23.1 GMAC MII Timings
        1. Table 7-67 Timing Requirements for miin_rxclk - MII Operation
        2. Table 7-68 Timing Requirements for miin_txclk - MII Operation
        3. Table 7-69 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
        4. Table 7-70 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
      2. 7.23.2 GMAC MDIO Interface Timings
      3. 7.23.3 GMAC RMII Timings
        1. Table 7-75 Timing Requirements for GMAC REF_CLK - RMII Operation
        2. Table 7-76 Timing Requirements for GMAC RMIIn Receive
        3. Table 7-77 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
        4. Table 7-78 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
      4. 7.23.4 GMAC RGMII Timings
        1. Table 7-82 Timing Requirements for rgmiin_rxc - RGMIIn Operation
        2. Table 7-83 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
        3. Table 7-84 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
        4. Table 7-85 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
    24. 7.24 eMMC/SD/SDIO
      1. 7.24.1 MMC1-SD Card Interface
        1. 7.24.1.1 Default speed, 4-bit data, SDR, half-cycle
        2. 7.24.1.2 High speed, 4-bit data, SDR, half-cycle
        3. 7.24.1.3 SDR12, 4-bit data, half-cycle
        4. 7.24.1.4 SDR25, 4-bit data, half-cycle
        5. 7.24.1.5 UHS-I SDR50, 4-bit data, half-cycle
        6. 7.24.1.6 UHS-I SDR104, 4-bit data, half-cycle
        7. 7.24.1.7 UHS-I DDR50, 4-bit data
      2. 7.24.2 MMC2 - eMMC
        1. 7.24.2.1 Standard JC64 SDR, 8-bit data, half cycle
        2. 7.24.2.2 High Speed JC64 SDR, 8-bit data, half cycle
        3. 7.24.2.3 High Speed HS200 JEDS84, 8-bit data, half cycle
        4. 7.24.2.4 High Speed JC64 DDR, 8-bit data
          1. Table 7-110 Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
      3. 7.24.3 MMC3 and MMC4-SDIO/SD
        1. 7.24.3.1 MMC3 and MMC4, SD Default Speed
        2. 7.24.3.2 MMC3 and MMC4, SD High Speed
        3. 7.24.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
        4. 7.24.3.4 MMC3 and MMC4, SD SDR25 Mode
        5. 7.24.3.5 MMC3 SDIO High Speed UHS-I SDR50 Mode, Half Cycle
    25. 7.25 General-Purpose Interface (GPIO)
    26. 7.26 PRU-ICSS Interfaces
      1. 7.26.1 Programmable Real-Time Unit (PRU-ICSS PRU)
        1. 7.26.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
          1. Table 7-132 PRU-ICSS PRU Timing Requirements - Direct Input Mode
          2. Table 7-133 PRU-ICSS PRU Switching Requirements - Direct Output Mode
        2. 7.26.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
          1. Table 7-134 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
        3. 7.26.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
          1. Table 7-135 PRU-ICSS PRU Timing Requirements - Shift In Mode
          2. Table 7-136 PRU-ICSS PRU Switching Requirements - Shift Out Mode
        4. 7.26.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
          1. Table 7-137 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
          2. Table 7-138 PRU-ICSS PRU Timing Requirements - EnDAT Mode
          3. Table 7-139 PRU-ICSS PRU Switching Requirements - EnDAT Mode
      2. 7.26.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
        1. 7.26.2.1 PRU-ICSS ECAT Electrical Data and Timing
          1. Table 7-140 PRU-ICSS ECAT Timing Requirements - Input Validated With LATCH_IN
          2. Table 7-141 PRU-ICSS ECAT Timing Requirements - Input Validated With SYNCx
          3. Table 7-142 PRU-ICSS ECAT Timing Requirements - Input Validated With Start of Frame (SOF)
          4. Table 7-143 PRU-ICSS ECAT Timing Requirements - LATCHx_IN
          5. Table 7-144 PRU-ICSS ECAT Switching Requirements - Digital IOs
      3. 7.26.3 PRU-ICSS MII_RT and Switch
        1. 7.26.3.1 PRU-ICSS MDIO Electrical Data and Timing
          1. Table 7-145 PRU-ICSS MDIO Timing Requirements - MDIO_DATA
          2. Table 7-146 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
          3. Table 7-147 PRU-ICSS MDIO Switching Characteristics - MDIO_DATA
        2. 7.26.3.2 PRU-ICSS MII_RT Electrical Data and Timing
          1. Table 7-148 PRU-ICSS MII_RT Timing Requirements - MII[x]_RXCLK
          2. Table 7-149 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
          3. Table 7-150 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
          4. Table 7-151 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
      4. 7.26.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
        1. Table 7-152 Timing Requirements for PRU-ICSS UART Receive
        2. Table 7-153 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
      5. 7.26.5 PRU-ICSS Manual Functional Mapping
    27. 7.27 System and Miscellaneous interfaces
    28. 7.28 Test Interfaces
      1. 7.28.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
        1. 7.28.1.1 JTAG Electrical Data/Timing
          1. Table 7-173 Timing Requirements for IEEE 1149.1 JTAG
          2. Table 7-174 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
          3. Table 7-175 Timing Requirements for IEEE 1149.1 JTAG With RTCK
          4. Table 7-176 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
      2. 7.28.2 Trace Port Interface Unit (TPIU)
        1. 7.28.2.1 TPIU PLL DDR Mode
  8. 8 Applications, Implementation, and Layout
    1. 8.1 Power Supply Mapping
    2. 8.2 DDR3 Board Design and Layout Guidelines
      1. 8.2.1 DDR3 General Board Layout Guidelines
      2. 8.2.2 DDR3 Board Design and Layout Guidelines
        1. 8.2.2.1  Board Designs
        2. 8.2.2.2  DDR3 EMIF
        3. 8.2.2.3  DDR3 Device Combinations
        4. 8.2.2.4  DDR3 Interface Schematic
          1. 8.2.2.4.1 32-Bit DDR3 Interface
          2. 8.2.2.4.2 16-Bit DDR3 Interface
        5. 8.2.2.5  Compatible JEDEC DDR3 Devices
        6. 8.2.2.6  PCB Stackup
        7. 8.2.2.7  Placement
        8. 8.2.2.8  DDR3 Keepout Region
        9. 8.2.2.9  Bulk Bypass Capacitors
        10. 8.2.2.10 High Speed Bypass Capacitors
          1. 8.2.2.10.1 Return Current Bypass Capacitors
        11. 8.2.2.11 Net Classes
        12. 8.2.2.12 DDR3 Signal Termination
        13. 8.2.2.13 VREF_DDR Routing
        14. 8.2.2.14 VTT
        15. 8.2.2.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 8.2.2.15.1 Four DDR3 Devices
            1. 8.2.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 8.2.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 8.2.2.15.2 Two DDR3 Devices
            1. 8.2.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 8.2.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 8.2.2.15.3 One DDR3 Device
            1. 8.2.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 8.2.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 8.2.2.16 Data Topologies and Routing Definition
          1. 8.2.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 8.2.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 8.2.2.17 Routing Specification
          1. 8.2.2.17.1 CK and ADDR_CTRL Routing Specification
          2. 8.2.2.17.2 DQS and DQ Routing Specification
    3. 8.3 High Speed Differential Signal Routing Guidance
    4. 8.4 Power Distribution Network Implementation Guidance
    5. 8.5 Thermal Solution Guidance
    6. 8.6 Single-Ended Interfaces
      1. 8.6.1 General Routing Guidelines
      2. 8.6.2 QSPI Board Design and Layout Guidelines
    7. 8.7 LJCB_REFN/P Connections
    8. 8.8 Clock Routing Guidelines
      1. 8.8.1 32-kHz Oscillator Routing
      2. 8.8.2 Oscillator Ground Connection
  9. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Related Links
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABC|760
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.4.24 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)

CAUTION

The I/O timing provided in Section 7, Timing Requirements and Switching Characteristics are valid only if signals within a single IOSET are used. The IOSETs are defined in the Table 7-154 and Table 7-155.

NOTE

For more information, see Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem chapter in the device TRM.

Table 4-27 PRU-ICSS Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL BOTTOM
PRU-ICSS 1
pr1_pru1_gpi0 PRU1 General-Purpose Input I E2
pr1_pru1_gpi1 PRU1 General-Purpose Input I D2
pr1_pru1_gpi10 PRU1 General-Purpose Input I C2
pr1_pru1_gpi11 PRU1 General-Purpose Input I C3
pr1_pru1_gpi12 PRU1 General-Purpose Input I C4
pr1_pru1_gpi13 PRU1 General-Purpose Input I B2
pr1_pru1_gpi14 PRU1 General-Purpose Input I D6
pr1_pru1_gpi15 PRU1 General-Purpose Input I C5
pr1_pru1_gpi16 PRU1 General-Purpose Input I A3
pr1_pru1_gpi17 PRU1 General-Purpose Input I B3
pr1_pru1_gpi18 PRU1 General-Purpose Input I B4
pr1_pru1_gpi19 PRU1 General-Purpose Input I B5
pr1_pru1_gpi2 PRU1 General-Purpose Input I F4
pr1_pru1_gpi20 PRU1 General-Purpose Input I A4
pr1_pru1_gpi3 PRU1 General-Purpose Input I C1
pr1_pru1_gpi4 PRU1 General-Purpose Input I E4
pr1_pru1_gpi5 PRU1 General-Purpose Input I F5
pr1_pru1_gpi6 PRU1 General-Purpose Input I E6
pr1_pru1_gpi7 PRU1 General-Purpose Input I D3
pr1_pru1_gpi8 PRU1 General-Purpose Input I F6
pr1_pru1_gpi9 PRU1 General-Purpose Input I D5
pr1_pru1_gpo0 PRU1 General-Purpose Output O E2
pr1_pru1_gpo1 PRU1 General-Purpose Output O D2
pr1_pru1_gpo10 PRU1 General-Purpose Output O C2
pr1_pru1_gpo11 PRU1 General-Purpose Output O C3
pr1_pru1_gpo12 PRU1 General-Purpose Output O C4
pr1_pru1_gpo13 PRU1 General-Purpose Output O B2
pr1_pru1_gpo14 PRU1 General-Purpose Output O D6
pr1_pru1_gpo15 PRU1 General-Purpose Output O C5
pr1_pru1_gpo16 PRU1 General-Purpose Output O A3
pr1_pru1_gpo17 PRU1 General-Purpose Output O B3
pr1_pru1_gpo18 PRU1 General-Purpose Output O B4
pr1_pru1_gpo19 PRU1 General-Purpose Output O B5
pr1_pru1_gpo2 PRU1 General-Purpose Output O F4
pr1_pru1_gpo20 PRU1 General-Purpose Output O A4
pr1_pru1_gpo3 PRU1 General-Purpose Output O C1
pr1_pru1_gpo4 PRU1 General-Purpose Output O E4
pr1_pru1_gpo5 PRU1 General-Purpose Output O F5
pr1_pru1_gpo6 PRU1 General-Purpose Output O E6
pr1_pru1_gpo7 PRU1 General-Purpose Output O D3
pr1_pru1_gpo8 PRU1 General-Purpose Output O F6
pr1_pru1_gpo9 PRU1 General-Purpose Output O D5
pr1_edc_latch0_in Latch Input 0 I E2
pr1_edc_sync0_out SYNC 0 Output O D2
pr1_edio_data_in0 Ethernet Digital Input I E1
pr1_edio_data_in1 Ethernet Digital Input I G2
pr1_edio_data_in2 Ethernet Digital Input I H7
pr1_edio_data_in3 Ethernet Digital Input I G1
pr1_edio_data_in4 Ethernet Digital Input I G6
pr1_edio_data_in5 Ethernet Digital Input I F2
pr1_edio_data_in6 Ethernet Digital Input I F3
pr1_edio_data_in7 Ethernet Digital Input I D1
pr1_edio_data_out0 Ethernet Digital Output O E1
pr1_edio_data_out1 Ethernet Digital Output O G2
pr1_edio_data_out2 Ethernet Digital Output O H7
pr1_edio_data_out3 Ethernet Digital Output O G1
pr1_edio_data_out4 Ethernet Digital Output O G6
pr1_edio_data_out5 Ethernet Digital Output O F2
pr1_edio_data_out6 Ethernet Digital Output O F3
pr1_edio_data_out7 Ethernet Digital Output O D1
pr1_edio_sof Start Of Frame O F4
pr1_mdio_data MDIO Data IO F6
pr1_mdio_mdclk MDIO Clock O D3
pr1_mii0_col MII0 Collision Detect I V1
pr1_mii0_crs MII0 Carrier Sense I V7
pr1_mii0_rxd0 MII0 Receive Data I U6
pr1_mii0_rxd1 MII0 Receive Data I V6
pr1_mii0_rxd2 MII0 Receive Data I V9
pr1_mii0_rxd3 MII0 Receive Data I W9
pr1_mii0_rxdv MII0 Data Valid I V2
pr1_mii0_rxer MII0 Receive Error I U7
pr1_mii0_rxlink MII0 Receive Link I U4
pr1_mii0_txd0 MII0 Transmit Data O W2
pr1_mii0_txd1 MII0 Transmit Data O Y2
pr1_mii0_txd2 MII0 Transmit Data O V4
pr1_mii0_txd3 MII0 Transmit Data O V5
pr1_mii0_txen MII0 Transmit Enable O V3
pr1_mii_mr0_clk MII0 Receive Clock I Y1
pr1_mii_mt0_clk MII0 Transmit Clock I U5
pr1_mii1_col MII1 Collision Detect I B5
pr1_mii1_crs MII1 Carrier Sense I A4
pr1_mii1_rxd0 MII1 Receive Data I A3
pr1_mii1_rxd1 MII1 Receive Data I C5
pr1_mii1_rxd2 MII1 Receive Data I D6
pr1_mii1_rxd3 MII1 Receive Data I B2
pr1_mii1_rxdv MII1 Data Valid I C4
pr1_mii1_rxer MII1 Receive Error I B3
pr1_mii1_rxlink MII1 Receive Link I B4
pr1_mii1_txd0 MII1 Transmit Data O C2
pr1_mii1_txd1 MII1 Transmit Data O D5
pr1_mii1_txd2 MII1 Transmit Data O E6
pr1_mii1_txd3 MII1 Transmit Data O F5
pr1_mii1_txen MII1 Transmit Enable O E4
pr1_mii_mr1_clk MII1 Receive Clock I C3
pr1_mii_mt1_clk MII1 Transmit Clock I C1
pr1_uart0_cts_n UART Clear-To-Send I F11,G1
pr1_uart0_rts_n UART Ready-To-Send O G10,G6
pr1_uart0_rxd UART Receive Data I F10,F2
pr1_uart0_txd UART Transmit Data O F3,G11
pr1_ecap0_ecap_capin_apwm_o Capture Input / PWM output IO D1,E9
PRU-ICSS 2
pr2_pru0_gpi0 PRU0 General-Purpose Input I AC5,G11
pr2_pru0_gpi1 PRU0 General-Purpose Input I AB4,E9
pr2_pru0_gpi10 PRU0 General-Purpose Input I AB8,C6
pr2_pru0_gpi11 PRU0 General-Purpose Input I AB5,C8
pr2_pru0_gpi12 PRU0 General-Purpose Input I B18,C7
pr2_pru0_gpi13 PRU0 General-Purpose Input I B7,F15
pr2_pru0_gpi14 PRU0 General-Purpose Input I B19,B8
pr2_pru0_gpi15 PRU0 General-Purpose Input I A7,C17
pr2_pru0_gpi16 PRU0 General-Purpose Input I A8,C15
pr2_pru0_gpi17 PRU0 General-Purpose Input I A16,C9
pr2_pru0_gpi18 PRU0 General-Purpose Input I A19,A9
pr2_pru0_gpi19 PRU0 General-Purpose Input I A18,B9
pr2_pru0_gpi2 PRU0 General-Purpose Input I AD4,F9
pr2_pru0_gpi20 PRU0 General-Purpose Input I A10,F14
pr2_pru0_gpi3 PRU0 General-Purpose Input I AC4,F8
pr2_pru0_gpi4 PRU0 General-Purpose Input I AC7,E7
pr2_pru0_gpi5 PRU0 General-Purpose Input I AC6,E8
pr2_pru0_gpi6 PRU0 General-Purpose Input I AC9,D9
pr2_pru0_gpi7 PRU0 General-Purpose Input I AC3,D7
pr2_pru0_gpi8 PRU0 General-Purpose Input I AC8,D8
pr2_pru0_gpi9 PRU0 General-Purpose Input I A5,AD6
pr2_pru1_gpi0 PRU1 General-Purpose Input I D17,V1
pr2_pru1_gpi1 PRU1 General-Purpose Input I AA3,U4
pr2_pru1_gpi10 PRU1 General-Purpose Input I B12,U6
pr2_pru1_gpi11 PRU1 General-Purpose Input I A11,U5
pr2_pru1_gpi12 PRU1 General-Purpose Input I B13,V5
pr2_pru1_gpi13 PRU1 General-Purpose Input I A12,V4
pr2_pru1_gpi14 PRU1 General-Purpose Input I E14,V3
pr2_pru1_gpi15 PRU1 General-Purpose Input I A13,Y2
pr2_pru1_gpi16 PRU1 General-Purpose Input I G14,W2
pr2_pru1_gpi17 PRU1 General-Purpose Input I E11
pr2_pru1_gpi18 PRU1 General-Purpose Input I F11
pr2_pru1_gpi19 PRU1 General-Purpose Input I G10
pr2_pru1_gpi2 PRU1 General-Purpose Input I AB9,U3
pr2_pru1_gpi20 PRU1 General-Purpose Input I F10
pr2_pru1_gpi3 PRU1 General-Purpose Input I AB3,V2
pr2_pru1_gpi4 PRU1 General-Purpose Input I AA4,Y1
pr2_pru1_gpi5 PRU1 General-Purpose Input I D18,W9
pr2_pru1_gpi6 PRU1 General-Purpose Input I E17,V9
pr2_pru1_gpi7 PRU1 General-Purpose Input I C14,V7
pr2_pru1_gpi8 PRU1 General-Purpose Input I G12,U7
pr2_pru1_gpi9 PRU1 General-Purpose Input I F12,V6
pr2_pru0_gpo0 PRU0 General-Purpose Output O AC5,G11
pr2_pru0_gpo1 PRU0 General-Purpose Output O AB4,E9
pr2_pru0_gpo10 PRU0 General-Purpose Output O AB8,C6
pr2_pru0_gpo11 PRU0 General-Purpose Output O AB5,C8
pr2_pru0_gpo12 PRU0 General-Purpose Output O B18,C7
pr2_pru0_gpo13 PRU0 General-Purpose Output O B7,F15
pr2_pru0_gpo14 PRU0 General-Purpose Output O B19,B8
pr2_pru0_gpo15 PRU0 General-Purpose Output O A7,C17
pr2_pru0_gpo16 PRU0 General-Purpose Output O A8,C15
pr2_pru0_gpo17 PRU0 General-Purpose Output O A16,C9
pr2_pru0_gpo18 PRU0 General-Purpose Output O A19,A9
pr2_pru0_gpo19 PRU0 General-Purpose Output O A18,B9
pr2_pru0_gpo2 PRU0 General-Purpose Output O AD4,F9
pr2_pru0_gpo20 PRU0 General-Purpose Output O A10,F14
pr2_pru0_gpo3 PRU0 General-Purpose Output O AC4,F8
pr2_pru0_gpo4 PRU0 General-Purpose Output O AC7,E7
pr2_pru0_gpo5 PRU0 General-Purpose Output O AC6,E8
pr2_pru0_gpo6 PRU0 General-Purpose Output O AC9,D9
pr2_pru0_gpo7 PRU0 General-Purpose Output O AC3,D7
pr2_pru0_gpo8 PRU0 General-Purpose Output O AC8,D8
pr2_pru0_gpo9 PRU0 General-Purpose Output O A5,AD6
pr2_pru1_gpo0 PRU1 General-Purpose Output O D17,V1
pr2_pru1_gpo1 PRU1 General-Purpose Output O AA3,U4
pr2_pru1_gpo10 PRU1 General-Purpose Output O B12,U6
pr2_pru1_gpo11 PRU1 General-Purpose Output O A11,U5
pr2_pru1_gpo12 PRU1 General-Purpose Output O B13,V5
pr2_pru1_gpo13 PRU1 General-Purpose Output O A12,V4
pr2_pru1_gpo14 PRU1 General-Purpose Output O E14,V3
pr2_pru1_gpo15 PRU1 General-Purpose Output O A13,Y2
pr2_pru1_gpo16 PRU1 General-Purpose Output O G14,W2
pr2_pru1_gpo17 PRU1 General-Purpose Output O E11
pr2_pru1_gpo18 PRU1 General-Purpose Output O F11
pr2_pru1_gpo19 PRU1 General-Purpose Output O G10
pr2_pru1_gpo2 PRU1 General-Purpose Output O AB9,U3
pr2_pru1_gpo20 PRU1 General-Purpose Output O F10
pr2_pru1_gpo3 PRU1 General-Purpose Output O AB3,V2
pr2_pru1_gpo4 PRU1 General-Purpose Output O AA4,Y1
pr2_pru1_gpo5 PRU1 General-Purpose Output O D18,W9
pr2_pru1_gpo6 PRU1 General-Purpose Output O E17,V9
pr2_pru1_gpo7 PRU1 General-Purpose Output O C14,V7
pr2_pru1_gpo8 PRU1 General-Purpose Output O G12,U7
pr2_pru1_gpo9 PRU1 General-Purpose Output O F12,V6
pr2_edc_latch0_in Latch Input 0 I F9
pr2_edc_latch1_in Latch Input 1 I F8
pr2_edc_sync0_out SYNC 0 Output O E7
pr2_edc_sync1_out SYNC 1 Output O E8
pr2_edio_data_in0 Ethernet Digital Input I B7
pr2_edio_data_in1 Ethernet Digital Input I B8
pr2_edio_data_in2 Ethernet Digital Input I A7
pr2_edio_data_in3 Ethernet Digital Input I A8
pr2_edio_data_in4 Ethernet Digital Input I C9
pr2_edio_data_in5 Ethernet Digital Input I A9
pr2_edio_data_in6 Ethernet Digital Input I B9
pr2_edio_data_in7 Ethernet Digital Input I A10
pr2_edio_data_out0 Ethernet Digital Output O B7
pr2_edio_data_out1 Ethernet Digital Output O B8
pr2_edio_data_out2 Ethernet Digital Output O A7
pr2_edio_data_out3 Ethernet Digital Output O A8
pr2_edio_data_out4 Ethernet Digital Output O C9
pr2_edio_data_out5 Ethernet Digital Output O A9
pr2_edio_data_out6 Ethernet Digital Output O B9
pr2_edio_data_out7 Ethernet Digital Output O A10
pr2_edio_latch_in Latch Input I D9
pr2_edio_sof Start Of Frame O D7
pr2_mdio_data MDIO Data IO AA4,D14
pr2_mdio_mdclk MDIO Clock O AB3,C14
pr2_mii0_col MII0 Collision Detect I F15
pr2_mii0_crs MII0 Carrier Sense I B18
pr2_mii0_rxd0 MII0 Receive Data I C15
pr2_mii0_rxd1 MII0 Receive Data I A18
pr2_mii0_rxd2 MII0 Receive Data I A19
pr2_mii0_rxd3 MII0 Receive Data I F14
pr2_mii0_rxdv MII0 Data Valid I G14
pr2_mii0_rxer MII0 Receive Error I G12
pr2_mii0_rxlink MII0 Receive Link I A16
pr2_mii0_txd0 MII0 Transmit Data O E14
pr2_mii0_txd1 MII0 Transmit Data O A12
pr2_mii0_txd2 MII0 Transmit Data O B13
pr2_mii0_txd3 MII0 Transmit Data O A11
pr2_mii0_txen MII0 Transmit Enable O B12
pr2_mii_mr0_clk MII0 Receive Clock I A13
pr2_mii_mt0_clk MII0 Transmit Clock I F12
pr2_mii1_col MII1 Collision Detect I D18
pr2_mii1_crs MII1 Carrier Sense I E17
pr2_mii1_rxd0 MII1 Receive Data I AB5
pr2_mii1_rxd1 MII1 Receive Data I AB8
pr2_mii1_rxd2 MII1 Receive Data I AD6
pr2_mii1_rxd3 MII1 Receive Data I AC8
pr2_mii1_rxdv MII1 Data Valid I AC3
pr2_mii1_rxer MII1 Receive Error I B19
pr2_mii1_rxlink MII1 Receive Link I C17
pr2_mii1_txd0 MII1 Transmit Data O AC6
pr2_mii1_txd1 MII1 Transmit Data O AC7
pr2_mii1_txd2 MII1 Transmit Data O AC4
pr2_mii1_txd3 MII1 Transmit Data O AD4
pr2_mii1_txen MII1 Transmit Enable O AB4
pr2_mii_mr1_clk MII1 Receive Clock I AC9
pr2_mii_mt1_clk MII1 Transmit Clock I AC5
pr2_uart0_cts_n UART Clear-To-Send I D8
pr2_uart0_rts_n UART Ready-To-Send O A5
pr2_uart0_rxd UART Receive Data I C6
pr2_uart0_txd UART Transmit Data O C8
pr2_ecap0_ecap_capin_apwm_o Capture Input / PWM output IO C7

NOTE

PRU-ICSS has an internal wrapper multiplexing that allows MII_RT, EnDAT®, and Sigma Delta functionality to be muxed with the PRU GPIO signals. See PRU-ICSS IO Interface in device TRM. Additionally, the EGPIO module can also be configured to export additional functions to EGPIO pins in place of simple GPIO. See Enhanced General-Purpose Module/Serial Capture Unit in device TRM.