SPRSP52C December   2019  – September 2023 AM6526 , AM6528 , AM6546 , AM6548

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1  ADC
        1. 5.3.1.1 MCU Domain
      2. 5.3.2  CAL
        1. 5.3.2.1 MAIN Domain
      3. 5.3.3  CPSW2G
        1. 5.3.3.1 MCU Domain
      4. 5.3.4  DDRSS
        1. 5.3.4.1 MAIN Domain
        2. 5.3.4.2 DDRSS Mapping
      5. 5.3.5  DMTIMER
        1. 5.3.5.1 MAIN Domain
        2. 5.3.5.2 MCU Domain
      6. 5.3.6  DSS
        1. 5.3.6.1 MAIN Domain
      7. 5.3.7  ECAP
        1. 5.3.7.1 MAIN Domain
      8. 5.3.8  EHRPWM
        1. 5.3.8.1 MAIN Domain
      9. 5.3.9  EQEP
        1. 5.3.9.1 MAIN Domain
      10. 5.3.10 GPIO
        1. 5.3.10.1 MAIN Domain
        2. 5.3.10.2 WKUP Domain
      11. 5.3.11 GPMC
        1. 5.3.11.1 MAIN Domain
      12. 5.3.12 HyperBus
        1. 5.3.12.1 MCU Domain
      13. 5.3.13 I2C
        1. 5.3.13.1 MAIN Domain
        2. 5.3.13.2 MCU Domain
        3. 5.3.13.3 WKUP Domain
      14. 5.3.14 MCAN
        1. 5.3.14.1 MCU Domain
      15. 5.3.15 MCASP
        1. 5.3.15.1 MAIN Domain
      16. 5.3.16 MCSPI
        1. 5.3.16.1 MAIN Domain
        2. 5.3.16.2 MCU Domain
      17. 5.3.17 MMCSD
        1. 5.3.17.1 MAIN Domain
      18. 5.3.18 CPTS
        1. 5.3.18.1 MCU Domain
        2. 5.3.18.2 MAIN Domain
      19. 5.3.19 OLDI
        1. 5.3.19.1 MAIN Domain
      20. 5.3.20 OSPI
        1. 5.3.20.1 MCU Domain
      21. 5.3.21 PRU_ICSSG
        1. 5.3.21.1 MAIN Domain
      22. 5.3.22 SERDES
        1. 5.3.22.1 MAIN Domain
      23. 5.3.23 UART
        1. 5.3.23.1 MAIN Domain
        2. 5.3.23.2 MCU Domain
        3. 5.3.23.3 WKUP Domain
      24. 5.3.24 USB
        1. 5.3.24.1 MAIN Domain
      25. 5.3.25 Emulation and Debug
        1. 5.3.25.1 MAIN Domain
      26. 5.3.26 System and Miscellaneous
        1. 5.3.26.1 Boot Mode Configuration
          1. 5.3.26.1.1 MAIN Domain
          2. 5.3.26.1.2 MCU Domain
        2. 5.3.26.2 Clock
          1. 5.3.26.2.1 MAIN Domain
          2. 5.3.26.2.2 WKUP Domain
        3. 5.3.26.3 System
          1. 5.3.26.3.1 MAIN Domain
          2. 5.3.26.3.2 WKUP Domain
        4. 5.3.26.4 Miscellaneous
          1. 5.3.26.4.1 WKUP Domain
        5. 5.3.26.5 EFUSE
          1. 5.3.26.5.1 MAIN Domain
          2. 5.3.26.5.2 MCU Domain
      27. 5.3.27 Power Supply
    4. 5.4 Pin Multiplexing
    5. 5.5 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Power-On Hours (POH)
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Operating Performance Points
      1. 6.5.1 Voltage and Core Clock Specifications
    6. 6.6 Electrical Characteristics
      1. 6.6.1 I2C OPEN DRAIN DC Electrical Characteristics
      2. 6.6.2 Analog OSC Buffers DC Electrical Characteristics
      3. 6.6.3 Analog ADC DC Electrical Characteristics
      4. 6.6.4 DPHY CSI2 Buffers DC Electrical Characteristics
      5. 6.6.5 OLDI LVDS Buffers DC Electrical Characteristics
        1. 6.6.5.1 LVCMOS Buffers DC Electrical Characteristics
      6. 6.6.6 USBHS Buffers DC Electrical Characteristics
      7. 6.6.7 SERDES Buffers DC Electrical Characteristics
    7. 6.7 VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.7.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.7.2 Hardware Requirements
      3. 6.7.3 Programming Sequence
      4. 6.7.4 Impact to Your Hardware Warranty
    8. 6.8 Thermal Resistance Characteristics
      1. 6.8.1 Thermal Resistance Characteristics
    9. 6.9 Timing and Switching Characteristics
      1. 6.9.1 Timing Parameters and Information
      2. 6.9.2 Power Supply Sequencing
        1. 6.9.2.1 Power Supply Slew Rate Requirement
        2. 6.9.2.2 VDDA_1P8_SERDES0 Supply Slew Rate Requirement
        3. 6.9.2.3 Power-Up Sequencing
        4. 6.9.2.4 Power-Down Sequencing
      3. 6.9.3 System Timing
        1. 6.9.3.1 Reset Electrical Data/Timing
        2. 6.9.3.2 Safety Signal Timing
        3. 6.9.3.3 Clock Timing
      4. 6.9.4 Clock Specifications
        1. 6.9.4.1 Input Clocks / Oscillators
          1. 6.9.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
          2. 6.9.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 6.9.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
          4. 6.9.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 6.9.4.1.5 Auxiliary OSC1 Not Used
          6. 6.9.4.1.6 WKUP_LFOSC0 Internal Oscillator Clock Source
          7. 6.9.4.1.7 WKUP_LFOSC0 LVCMOS Digital Clock Source
          8. 6.9.4.1.8 WKUP_LFOSC0 Not Used
        2. 6.9.4.2 Output Clocks
        3. 6.9.4.3 PLLs
        4. 6.9.4.4 Recommended Clock and Control Signal Transition Behavior
        5. 6.9.4.5 Module and Peripheral Clock Frequencies
      5. 6.9.5 Peripherals
        1. 6.9.5.1  VIN
        2. 6.9.5.2  CPSW2G
          1. 6.9.5.2.1 CPSW2G MDIO Interface Timings
          2. 6.9.5.2.2 CPSW2G RMII Timings
            1. 6.9.5.2.2.1 Timing Requirements for RMII[x]_REFCLK - RMII Mode
            2. 6.9.5.2.2.2 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
            3. 6.9.5.2.2.3 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
          3. 6.9.5.2.3 CPSW2G RGMII Timings
            1. 6.9.5.2.3.1 Timing Requirements for RGMII[x]_RCLK - RGMII Mode
            2. 6.9.5.2.3.2 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
            3. 6.9.5.2.3.3 Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
            4. 6.9.5.2.3.4 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL - RGMII Mode
        3. 6.9.5.3  CSI2
        4. 6.9.5.4  DDRSS
        5. 6.9.5.5  DSS
        6. 6.9.5.6  eCAP
          1. 6.9.5.6.1 eCAP Timing Requirements
          2. 6.9.5.6.2 eCAP Switching Characteristics
        7. 6.9.5.7  ePWM
          1. 6.9.5.7.1 ePWM Timing Requirements
          2. 6.9.5.7.2 ePWM Switching Characteristics
        8. 6.9.5.8  eQEP
          1. 6.9.5.8.1 eQEP Timing Requirements
          2. 6.9.5.8.2 eQEP Switching Characteristics
        9. 6.9.5.9  GPIO
          1. 6.9.5.9.1 GPIO Timing Requirements
          2. 6.9.5.9.2 GPIO Switching Characteristics
        10. 6.9.5.10 GPMC
          1. 6.9.5.10.1 GPMC and NOR Flash—Synchronous Mode
            1. 6.9.5.10.1.1 GPMC and NOR Flash Timing Requirements—Synchronous Mode
            2. 6.9.5.10.1.2 GPMC and NOR Flash Switching Characteristics—Synchronous Mode
          2. 6.9.5.10.2 GPMC and NOR Flash—Asynchronous Mode
            1. 6.9.5.10.2.1 GPMC and NOR Flash Timing Requirements—Asynchronous Mode
            2. 6.9.5.10.2.2 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
          3. 6.9.5.10.3 GPMC and NAND Flash—Asynchronous Mode
            1. 6.9.5.10.3.1 GPMC and NAND Flash Timing Requirements—Asynchronous Mode
            2. 6.9.5.10.3.2 GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
        11. 6.9.5.11 HyperBus
          1. 6.9.5.11.1 Timing Requirements for HyperBus Initialization
          2. 6.9.5.11.2 HyperBus 166 MHz Switching Characteristics
          3. 6.9.5.11.3 HyperBus 100 MHz Switching Characteristics
        12. 6.9.5.12 I2C
        13. 6.9.5.13 MCAN
        14. 6.9.5.14 MCASP
          1. 6.9.5.14.1 MCASP Timing Requirements and Switching Characteristics
        15. 6.9.5.15 MCSPI
          1. 6.9.5.15.1 SPI—Master Mode
          2. 6.9.5.15.2 SPI—Slave Mode
        16. 6.9.5.16 MMCSD
          1. 6.9.5.16.1 MMCSDi — eMMC/SD/SDIO Card Interface
            1. 6.9.5.16.1.1 Default Speed, 3.3V Legacy SDR Mode
            2. 6.9.5.16.1.2 High Speed, 3.3V High Speed SDR Mode
            3. 6.9.5.16.1.3 UHS-I SDR12, 1.8-V Legacy SDR Mode
            4. 6.9.5.16.1.4 UHS-I SDR25 Mode
            5. 6.9.5.16.1.5 UHS-I DDR50 Mode
            6. 6.9.5.16.1.6 UHS-I SDR50 Mode
            7. 6.9.5.16.1.7 UHS-I SDR104 / HS200 Mode
        17. 6.9.5.17 CPTS
          1. 6.9.5.17.1 CPTS Timing Requirements
          2. 6.9.5.17.2 CPTS Switching Characteristics
        18. 6.9.5.18 OSPI
          1. 6.9.5.18.1 OSPI with Data Training
            1. 6.9.5.18.1.1 OSPI Switching Characteristics - Data Training
          2. 6.9.5.18.2 OSPI without Data Training
            1. 6.9.5.18.2.1 OSPI Timing Requirements - SDR Mode
            2. 6.9.5.18.2.2 OSPI Switching Characteristics - SDR Mode
            3. 6.9.5.18.2.3 OSPI Timing Requirements - DDR Mode
            4. 6.9.5.18.2.4 OSPI Switching Characteristics - DDR Mode
        19. 6.9.5.19 OLDI
          1. 6.9.5.19.1 OLDI Switching Characteristics
        20. 6.9.5.20 PCIE
        21. 6.9.5.21 PRU_ICSSG
          1. 6.9.5.21.1 Programmable Real-Time Unit (PRU_ICSSG PRU)
            1. 6.9.5.21.1.1 PRU_ICSSG PRU Direct Input/Output Mode Electrical Data and Timing
              1. 6.9.5.21.1.1.1 PRU_ICSSG PRU Switching Characteristics - Direct Output Mode
            2. 6.9.5.21.1.2 PRU_ICSSG PRU Parallel Capture Mode Electrical Data and Timing
              1. 6.9.5.21.1.2.1 PRU_ICSSG PRU Timing Requirements - Parallel Capture Mode
            3. 6.9.5.21.1.3 PRU_ICSSG PRU Shift Mode Electrical Data and Timing
              1. 6.9.5.21.1.3.1 PRU_ICSSG PRU Timing Requirements - Shift In Mode
              2. 6.9.5.21.1.3.2 PRU_ICSSG PRU Switching Characteristics - Shift Out Mode
            4. 6.9.5.21.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Modes Electrical Data and Timing
              1. 6.9.5.21.1.4.1 PRU_ICSSG PRU Timing Requirements - Sigma Delta Mode
              2. 6.9.5.21.1.4.2 PRU_ICSSG PRU Timing Requirements - Peripheral Interface Mode
              3. 6.9.5.21.1.4.3 PRU_ICSSG PRU Switching Characteristics - Peripheral Interface Mode
          2. 6.9.5.21.2 PRU_ICSSG Pulse Width Modulation (PWM)
            1. 6.9.5.21.2.1 PRU_ICSSG PWM Electrical Data and Timing
              1. 6.9.5.21.2.1.1 PRU_ICSSG PWM Switching Characteristics
          3. 6.9.5.21.3 PRU_ICSSG Industrial Ethernet Peripheral (PRU_ICSSG IEP)
            1. 6.9.5.21.3.1 PRU_ICSSG IEP Electrical Data and Timing
              1. 6.9.5.21.3.1.1 PRU_ICSSG IEP Timing Requirements - Input Validated with SYNCx
              2. 6.9.5.21.3.1.2 PRU_ICSSG IEP Timing Requirements - Digital IOs
              3. 6.9.5.21.3.1.3 PRU_ICSSG IEP Timing Requirements - LATCHx_IN
          4. 6.9.5.21.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
            1. 6.9.5.21.4.1 PRU_ICSSG UART Electrical Data and Timing
              1. 6.9.5.21.4.1.1 PRU_ICSSG UART Timing Requirements
              2. 6.9.5.21.4.1.2 PRU_ICSSG UART Switching Characteristics
          5. 6.9.5.21.5 PRU_ICSSG Enhanced Capture Peripheral (PRU-ICSS ECAP)
            1. 6.9.5.21.5.1 PRU_ICSSG ECAP Electrical Data and Timing
              1. 6.9.5.21.5.1.1 PRU_ICSSG ECAP Timing Requirements
              2. 6.9.5.21.5.1.2 PRU_ICSSG ECAP Switching Characteristics
          6. 6.9.5.21.6 PRU_ICSSG RGMII, MII_RT, and Switch
            1. 6.9.5.21.6.1 PRU_ICSSG MDIO Electrical Data and Timing
              1. 6.9.5.21.6.1.1 PRU_ICSSG MDIO Timing Requirements
              2. 6.9.5.21.6.1.2 PRU_ICSSG MDIO Switching Characteristics - MDIO_CLK
              3. 6.9.5.21.6.1.3 PRU_ICSSG MDIO Switching Characteristics – MDIO_DATA
            2. 6.9.5.21.6.2 PRU_ICSSG RGMII Electrical Data and Timing
              1. 6.9.5.21.6.2.1 PRU_ICSSG RGMII Timing Requirements - RGMII_RXC
              2. 6.9.5.21.6.2.2 PRU_ICSSG RGMII Timing Requirements - RGMII_RD[3:0] and RGMII_RX_CTL
              3. 6.9.5.21.6.2.3 PRU_ICSSG RGMII Switching Characteristics - RGMII_TXC
              4. 6.9.5.21.6.2.4 PRU_ICSSG RGMII Switching Characteristics - RGMII_TD[3:0] and RGMII_TX_CTL
            3. 6.9.5.21.6.3 PRU_ICSSG MII_RT Electrical Data and Timing
              1. 6.9.5.21.6.3.1 PRU_ICSSG MII_RT Timing Requirements – MII_RX_CLK
              2. 6.9.5.21.6.3.2 PRU_ICSSG MII_RT Timing Requirements – MII_RXD[3:0], MII_RX_DV, and MII_RX_ER
              3. 6.9.5.21.6.3.3 PRU_ICSSG MII_RT Switching Characteristics – MII_TX_CLK
              4. 6.9.5.21.6.3.4 PRU_ICSSG MII_RT Switching Characteristics – MII_TXD[3:0] and MII_TXEN
        22. 6.9.5.22 Timers
          1. 6.9.5.22.1 Timing Requirements for Timers
          2. 6.9.5.22.2 Switching Characteristics for Timers
        23. 6.9.5.23 UART
          1. 6.9.5.23.1 Timing Requirements for UART
          2. 6.9.5.23.2 Switching Characteristics Over Recommended Operating Conditions for UART
        24. 6.9.5.24 USB
        25. 6.9.5.25 Emulation and Debug
          1. 6.9.5.25.1 Debug Trace
          2. 6.9.5.25.2 JTAG
            1. 6.9.5.25.2.1 JTAG Electrical Data and Timing
              1. 6.9.5.25.2.1.1 JTAG Timing Requirements
              2. 6.9.5.25.2.1.2 JTAG Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-A53
      2. 7.2.2 Arm Cortex-R5F
    3. 7.3 Accelerators and Coprocessors
      1. 7.3.1 PRU_ICSSG
        1. 7.3.1.1 PRU_ICSSG PRU and RTU_PRU Cores
        2. 7.3.1.2 PRU_ICSSG Broadside Accelerators Overview
        3. 7.3.1.3 PRU_ICSSG UART Module
        4. 7.3.1.4 PRU_ICSSG ECAP Module
        5. 7.3.1.5 PRU_ICSSG PWM Module
        6. 7.3.1.6 PRU_ICSSG MII_G_RT Module
        7. 7.3.1.7 PRU_ICSSG MII MDIO Module
        8. 7.3.1.8 PRU_ICSSG IEP
      2. 7.3.2 GPU
    4. 7.4 Other Subsystems
      1. 7.4.1 DMSC
      2. 7.4.2 MSMC
      3. 7.4.3 NAVSS
        1. 7.4.3.1 NAVSS0
        2. 7.4.3.2 MCU_NAVSS0
      4. 7.4.4 PDMA Controller
      5. 7.4.5 Peripherals
        1. 7.4.5.1  ADC
        2. 7.4.5.2  CAL
        3. 7.4.5.3  CPSW2G
        4. 7.4.5.4  DCC
        5. 7.4.5.5  DDRSS
        6. 7.4.5.6  DSS
        7. 7.4.5.7  ЕCAP
        8. 7.4.5.8  EPWM
        9. 7.4.5.9  ELM
        10. 7.4.5.10 ESM
        11. 7.4.5.11 EQEP
        12. 7.4.5.12 GPIO
        13. 7.4.5.13 GPMC
        14. 7.4.5.14 HyperBus
        15. 7.4.5.15 I2C
        16. 7.4.5.16 MCAN
        17. 7.4.5.17 MCASP
        18. 7.4.5.18 MCRC
        19. 7.4.5.19 MCSPI
        20. 7.4.5.20 MMCSD
        21. 7.4.5.21 OSPI
        22. 7.4.5.22 PCIE
        23. 7.4.5.23 SerDes
        24. 7.4.5.24 RTI
        25. 7.4.5.25 Timers
        26. 7.4.5.26 UART
        27. 7.4.5.27 USB
    5. 7.5 Identification
      1. 7.5.1 Revision Identification
      2. 7.5.2 Die Identification
      3. 7.5.3 JTAG Identification
      4. 7.5.4 ROM Code Identification
    6. 7.6 Boot Modes
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 Power Supply Decoupling and Bulk Capacitors
        1. 8.1.1.1 Power Distribution Network Implementation Guidance
      2. 8.1.2 External Oscillator
      3. 8.1.3 JTAG and EMU
      4. 8.1.4 Reset
      5. 8.1.5 Unused Pins
      6. 8.1.6 Hardware Design Guide for AM65x/DRA80xM Devices
    2. 8.2 Peripheral- and Interface-Specific Design Information
      1. 8.2.1 DDR Board Design and Layout Guidelines
      2. 8.2.2 OSPI Board Design and Layout Guidelines
        1. 8.2.2.1 No Loopback and Internal Pad Loopback
        2. 8.2.2.2 External Board Loopback
        3. 8.2.2.3 DQS (Only Available in Octal Flash Devices)
      3. 8.2.3 USB Design Guidelines
      4. 8.2.4 High Speed Differential Signal Routing Guidance
      5. 8.2.5 System Power Supply Monitor Design Guidelines
      6. 8.2.6 MMC Design Guidelines
      7. 8.2.7 Integrated Power Management Features
      8. 8.2.8 External Capacitors
        1. 8.2.8.1 LVCMOS External Capacitor Connections
      9. 8.2.9 Thermal Solution Guidance
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ACD|784
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.3.21.1 MAIN Domain

Note:

The PRU_ICSSG contains a second layer of multiplexing to enable additional functionality on the PRU GPO and GPI signals. This internal wrapper multiplexing is described in the PRU_ICSSG chapter in the device TRM.

Table 5-53 PRU_ICSSG0 Signal Descriptions
SIGNAL NAME [1]DESCRIPTION [2]PIN TYPE [3]BALL [4]
PRG0_ECAP0_IN_APWM_OUTPRU_ICSSG Enhanced Capture (ECAP) Input or Auxiliary PWM (APWM) OuputIOV25
PRG0_ECAP0_SYNC_INPRU_ICSSG ECAP Sync InputIU27
PRG0_ECAP0_SYNC_OUTPRU_ICSSG ECAP Sync OutputOU26
PRG0_IEP0_EDIO_OUTVALIDPRU_ICSSG Industrial Ethernet Digital I/O OutvalidOAD12
PRG0_IEP0_EDC_LATCH_IN0PRU_ICSSG Industrial Ethernet Distributed Clock Latch InputIV25
PRG0_IEP0_EDC_LATCH_IN1PRU_ICSSG Industrial Ethernet Distributed Clock Latch InputIU27
PRG0_IEP0_EDC_SYNC_OUT0PRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputOU24
PRG0_IEP0_EDC_SYNC_OUT1PRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputOU26
PRG0_IEP0_EDIO_DATA_IN_OUT28PRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputIOV26
PRG0_IEP0_EDIO_DATA_IN_OUT29PRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputIOU25
PRG0_IEP0_EDIO_DATA_IN_OUT30PRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputIOY28
PRG0_IEP0_EDIO_DATA_IN_OUT31PRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputIOAA28
PRG0_IEP1_EDC_LATCH_IN0PRU_ICSSG Industrial Ethernet Distributed Clock Latch InputIY26
PRG0_IEP1_EDC_LATCH_IN1PRU_ICSSG Industrial Ethernet Distributed Clock Latch InputIW28
PRG0_IEP1_EDC_SYNC_OUT0PRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputOW26
PRG0_IEP1_EDC_SYNC_OUT1PRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputOY27
PRG0_MDIO0_MDCPRU_ICSSG MDIO ClockOAE28
PRG0_MDIO0_MDIOPRU_ICSSG MDIO DataIOAE26
PRG0_PRU0_GPI0PRU_ICSSG PRU Data InputIV24
PRG0_PRU0_GPI1PRU_ICSSG PRU Data InputIW25
PRG0_PRU0_GPI2PRU_ICSSG PRU Data InputIW24
PRG0_PRU0_GPI3PRU_ICSSG PRU Data InputIAA27
PRG0_PRU0_GPI4PRU_ICSSG PRU Data InputIY24
PRG0_PRU0_GPI5PRU_ICSSG PRU Data InputIV28
PRG0_PRU0_GPI6PRU_ICSSG PRU Data InputIY25
PRG0_PRU0_GPI7PRU_ICSSG PRU Data InputIU27
PRG0_PRU0_GPI8PRU_ICSSG PRU Data InputIV27
PRG0_PRU0_GPI9PRU_ICSSG PRU Data InputIV26
PRG0_PRU0_GPI10PRU_ICSSG PRU Data InputIU25
PRG0_PRU0_GPI11PRU_ICSSG PRU Data InputIAB25
PRG0_PRU0_GPI12PRU_ICSSG PRU Data InputIAD27
PRG0_PRU0_GPI13PRU_ICSSG PRU Data InputIAC26
PRG0_PRU0_GPI14PRU_ICSSG PRU Data InputIAD26
PRG0_PRU0_GPI15PRU_ICSSG PRU Data InputIAA24
PRG0_PRU0_GPI16PRU_ICSSG PRU Data InputIAD28
PRG0_PRU0_GPI17PRU_ICSSG PRU Data InputIU26
PRG0_PRU0_GPI18PRU_ICSSG PRU Data InputIV25
PRG0_PRU0_GPI19PRU_ICSSG PRU Data InputIU24
PRG0_PRU0_GPO0PRU_ICSSG PRU Data OutputIOV24
PRG0_PRU0_GPO1PRU_ICSSG PRU Data OutputIOW25
PRG0_PRU0_GPO2PRU_ICSSG PRU Data OutputIOW24
PRG0_PRU0_GPO3PRU_ICSSG PRU Data OutputIOAA27
PRG0_PRU0_GPO4PRU_ICSSG PRU Data OutputIOY24
PRG0_PRU0_GPO5PRU_ICSSG PRU Data OutputIOV28
PRG0_PRU0_GPO6PRU_ICSSG PRU Data OutputIOY25
PRG0_PRU0_GPO7PRU_ICSSG PRU Data OutputIOU27
PRG0_PRU0_GPO8PRU_ICSSG PRU Data OutputIOV27
PRG0_PRU0_GPO9PRU_ICSSG PRU Data OutputIOV26
PRG0_PRU0_GPO10PRU_ICSSG PRU Data OutputIOU25
PRG0_PRU0_GPO11PRU_ICSSG PRU Data OutputIOAB25, AD27
PRG0_PRU0_GPO12PRU_ICSSG PRU Data OutputIOAC26, AD27
PRG0_PRU0_GPO13PRU_ICSSG PRU Data OutputIOAC26, AD26
PRG0_PRU0_GPO14PRU_ICSSG PRU Data OutputIOAA24, AD26
PRG0_PRU0_GPO15PRU_ICSSG PRU Data OutputIOAA24, AB25
PRG0_PRU0_GPO16PRU_ICSSG PRU Data OutputIOAD28
PRG0_PRU0_GPO17PRU_ICSSG PRU Data OutputIOU26
PRG0_PRU0_GPO18PRU_ICSSG PRU Data OutputIOV25
PRG0_PRU0_GPO19PRU_ICSSG PRU Data OutputIOU24
PRG0_PRU1_GPI0PRU_ICSSG PRU Data InputIAB28
PRG0_PRU1_GPI1PRU_ICSSG PRU Data InputIAC28
PRG0_PRU1_GPI2PRU_ICSSG PRU Data InputIAC27
PRG0_PRU1_GPI3PRU_ICSSG PRU Data InputIAB26
PRG0_PRU1_GPI4PRU_ICSSG PRU Data InputIAA25
PRG0_PRU1_GPI5PRU_ICSSG PRU Data InputIU23
PRG0_PRU1_GPI6PRU_ICSSG PRU Data InputIAB27
PRG0_PRU1_GPI7PRU_ICSSG PRU Data InputIW28
PRG0_PRU1_GPI8PRU_ICSSG PRU Data InputIW27
PRG0_PRU1_GPI9PRU_ICSSG PRU Data InputIY28
PRG0_PRU1_GPI10PRU_ICSSG PRU Data InputIAA28
PRG0_PRU1_GPI11PRU_ICSSG PRU Data InputIAB24
PRG0_PRU1_GPI12PRU_ICSSG PRU Data InputIAC25
PRG0_PRU1_GPI13PRU_ICSSG PRU Data InputIAD25
PRG0_PRU1_GPI14PRU_ICSSG PRU Data InputIAD24
PRG0_PRU1_GPI15PRU_ICSSG PRU Data InputIAE27
PRG0_PRU1_GPI16PRU_ICSSG PRU Data InputIAC24
PRG0_PRU1_GPI17PRU_ICSSG PRU Data InputIY27
PRG0_PRU1_GPI18PRU_ICSSG PRU Data InputIY26
PRG0_PRU1_GPI19PRU_ICSSG PRU Data InputIW26
PRG0_PRU1_GPO0PRU_ICSSG PRU Data OutputIOAB28
PRG0_PRU1_GPO1PRU_ICSSG PRU Data OutputIOAC28
PRG0_PRU1_GPO2PRU_ICSSG PRU Data OutputIOAC27
PRG0_PRU1_GPO3PRU_ICSSG PRU Data OutputIOAB26
PRG0_PRU1_GPO4PRU_ICSSG PRU Data OutputIOAA25
PRG0_PRU1_GPO5PRU_ICSSG PRU Data OutputIOU23
PRG0_PRU1_GPO6PRU_ICSSG PRU Data OutputIOAB27
PRG0_PRU1_GPO7PRU_ICSSG PRU Data OutputIOW28
PRG0_PRU1_GPO8PRU_ICSSG PRU Data OutputIOW27
PRG0_PRU1_GPO9PRU_ICSSG PRU Data OutputIOY28
PRG0_PRU1_GPO10PRU_ICSSG PRU Data OutputIOAA28
PRG0_PRU1_GPO11PRU_ICSSG PRU Data OutputIOAB24, AC25
PRG0_PRU1_GPO12PRU_ICSSG PRU Data OutputIOAC25, AD25
PRG0_PRU1_GPO13PRU_ICSSG PRU Data OutputIOAD24, AD25
PRG0_PRU1_GPO14PRU_ICSSG PRU Data OutputIOAD24, AE27
PRG0_PRU1_GPO15PRU_ICSSG PRU Data OutputIOAB24, AE27
PRG0_PRU1_GPO16PRU_ICSSG PRU Data OutputIOAC24
PRG0_PRU1_GPO17PRU_ICSSG PRU Data OutputIOY27
PRG0_PRU1_GPO18PRU_ICSSG PRU Data OutputIOY26
PRG0_PRU1_GPO19PRU_ICSSG PRU Data OutputIOW26
PRG0_PWM0_TZ_INPRU_ICSSG PWM Trip Zone InputIV25
PRG0_PWM0_TZ_OUTPRU_ICSSG PWM Trip Zone OutputOU24
PRG0_PWM1_TZ_INPRU_ICSSG PWM Trip Zone InputIY26
PRG0_PWM1_TZ_OUTPRU_ICSSG PWM Trip Zone OutputOW26
PRG0_PWM2_TZ_INPRU_ICSSG PWM Trip Zone InputIAA28
PRG0_PWM2_TZ_OUTPRU_ICSSG PWM Trip Zone OutputOW27
PRG0_PWM3_TZ_INPRU_ICSSG PWM Trip Zone InputIV26
PRG0_PWM3_TZ_OUTPRU_ICSSG PWM Trip Zone OutputOAB25
PRG0_PWM0_A0PRU_ICSSG PWM Output AIOAD27
PRG0_PWM0_A1PRU_ICSSG PWM Output AIOAD26
PRG0_PWM0_A2PRU_ICSSG PWM Output AIOAD28
PRG0_PWM0_B0PRU_ICSSG PWM Output BIOAC26
PRG0_PWM0_B1PRU_ICSSG PWM Output BIOAA24
PRG0_PWM0_B2PRU_ICSSG PWM Output BIOU26
PRG0_PWM1_A0PRU_ICSSG PWM Output AIOAC25
PRG0_PWM1_A1PRU_ICSSG PWM Output AIOAD24
PRG0_PWM1_A2PRU_ICSSG PWM Output AIOAC24
PRG0_PWM1_B0PRU_ICSSG PWM Output BIOAD25
PRG0_PWM1_B1PRU_ICSSG PWM Output BIOAE27
PRG0_PWM1_B2PRU_ICSSG PWM Output BIOY27
PRG0_PWM2_A0PRU_ICSSG PWM Output AIOW24
PRG0_PWM2_A1PRU_ICSSG PWM Output AIOV27
PRG0_PWM2_A2PRU_ICSSG PWM Output AIOAC27
PRG0_PWM2_B0PRU_ICSSG PWM Output BIOY24
PRG0_PWM2_B1PRU_ICSSG PWM Output BIOU25
PRG0_PWM2_B2PRU_ICSSG PWM Output BIOAA25
PRG0_PWM3_A0PRU_ICSSG PWM Output AIOV24
PRG0_PWM3_A1PRU_ICSSG PWM Output AIOY25
PRG0_PWM3_A2PRU_ICSSG PWM Output AIOAA27
PRG0_PWM3_B0PRU_ICSSG PWM Output BIOW25
PRG0_PWM3_B1PRU_ICSSG PWM Output BIOU27
PRG0_PWM3_B2PRU_ICSSG PWM Output BIOV28
PRG0_RGMII1_RXCPRU_ICSSG RGMII Receive ClockIY25
PRG0_RGMII1_RX_CTLPRU_ICSSG RGMII Receive ControlIY24
PRG0_RGMII1_TXCPRU_ICSSG RGMII Transmit ClockIOAD28
PRG0_RGMII1_TX_CTLPRU_ICSSG RGMII Transmit ControlOAB25
PRG0_RGMII2_RXCPRU_ICSSG RGMII Receive ClockIAB27
PRG0_RGMII2_RX_CTLPRU_ICSSG RGMII Receive ControlIAA25
PRG0_RGMII2_TXCPRU_ICSSG RGMII Transmit ClockIOAC24
PRG0_RGMII2_TX_CTLPRU_ICSSG RGMII Transmit ControlOAB24
PRG0_RGMII1_RD0PRU_ICSSG RGMII Receive DataIV24
PRG0_RGMII1_RD1PRU_ICSSG RGMII Receive DataIW25
PRG0_RGMII1_RD2PRU_ICSSG RGMII Receive DataIW24
PRG0_RGMII1_RD3PRU_ICSSG RGMII Receive DataIAA27
PRG0_RGMII1_TD0PRU_ICSSG RGMII Transmit DataOAD27
PRG0_RGMII1_TD1PRU_ICSSG RGMII Transmit DataOAC26
PRG0_RGMII1_TD2PRU_ICSSG RGMII Transmit DataOAD26
PRG0_RGMII1_TD3PRU_ICSSG RGMII Transmit DataOAA24
PRG0_RGMII2_RD0PRU_ICSSG RGMII Receive DataIAB28
PRG0_RGMII2_RD1PRU_ICSSG RGMII Receive DataIAC28
PRG0_RGMII2_RD2PRU_ICSSG RGMII Receive DataIAC27
PRG0_RGMII2_RD3PRU_ICSSG RGMII Receive DataIAB26
PRG0_RGMII2_TD0PRU_ICSSG RGMII Transmit DataOAC25
PRG0_RGMII2_TD1PRU_ICSSG RGMII Transmit DataOAD25
PRG0_RGMII2_TD2PRU_ICSSG RGMII Transmit DataOAD24
PRG0_RGMII2_TD3PRU_ICSSG RGMII Transmit DataOAE27
PRG0_UART0_CTSnPRU_ICSSG UART Clear to Send (active low)IV26
PRG0_UART0_RTSnPRU_ICSSG UART Request to Send (active low)OU25
PRG0_UART0_RXDPRU_ICSSG UART Receive DataIY28
PRG0_UART0_TXDPRU_ICSSG UART Transmit DataOAA28
Table 5-54 PRU_ICSSG1 Signal Descriptions
SIGNAL NAME [1]DESCRIPTION [2]PIN TYPE [3]BALL [4]
PRG1_ECAP0_IN_APWM_OUTPRU_ICSSG Enhanced Capture (ECAP) Input or Auxiliary PWM (APWM) OuputIOAC21
PRG1_ECAP0_SYNC_INPRU_ICSSG ECAP Sync InputIAD22
PRG1_ECAP0_SYNC_OUTPRU_ICSSG ECAP Sync OutputOAE23
PRG1_IEP0_EDIO_OUTVALIDPRU_ICSSG Industrial Ethernet Digital I/O OutvalidOAF13
PRG1_IEP0_EDC_LATCH_IN0PRU_ICSSG Industrial Ethernet Distributed Clock Latch InputIAG25
PRG1_IEP0_EDC_LATCH_IN1PRU_ICSSG Industrial Ethernet Distributed Clock Latch InputIAG27
PRG1_IEP0_EDC_SYNC_OUT0PRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputOAG26
PRG1_IEP0_EDC_SYNC_OUT1PRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputOAH26
PRG1_IEP0_EDIO_DATA_IN_OUT28PRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputIOAF26
PRG1_IEP0_EDIO_DATA_IN_OUT29PRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputIOAH25
PRG1_IEP0_EDIO_DATA_IN_OUT30PRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputIOAF25
PRG1_IEP0_EDIO_DATA_IN_OUT31PRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputIOAF24
PRG1_IEP1_EDC_LATCH_IN0PRU_ICSSG Industrial Ethernet Distributed Clock Latch InputIAD22
PRG1_IEP1_EDC_LATCH_IN1PRU_ICSSG Industrial Ethernet Distributed Clock Latch InputIAD23
PRG1_IEP1_EDC_SYNC_OUT0PRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputOAC21
PRG1_IEP1_EDC_SYNC_OUT1PRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputOAE23
PRG1_MDIO0_MDCPRU_ICSSG MDIO ClockOAH18
PRG1_MDIO0_MDIOPRU_ICSSG MDIO DataIOAD18
PRG1_PRU0_GPI0PRU_ICSSG PRU Data InputIAE22
PRG1_PRU0_GPI1PRU_ICSSG PRU Data InputIAG24
PRG1_PRU0_GPI2PRU_ICSSG PRU Data InputIAF23
PRG1_PRU0_GPI3PRU_ICSSG PRU Data InputIAD21
PRG1_PRU0_GPI4PRU_ICSSG PRU Data InputIAG23
PRG1_PRU0_GPI5PRU_ICSSG PRU Data InputIAF27
PRG1_PRU0_GPI6PRU_ICSSG PRU Data InputIAF22
PRG1_PRU0_GPI7PRU_ICSSG PRU Data InputIAG27
PRG1_PRU0_GPI8PRU_ICSSG PRU Data InputIAF28
PRG1_PRU0_GPI9PRU_ICSSG PRU Data InputIAF26
PRG1_PRU0_GPI10PRU_ICSSG PRU Data InputIAH25
PRG1_PRU0_GPI11PRU_ICSSG PRU Data InputIAF21
PRG1_PRU0_GPI12PRU_ICSSG PRU Data InputIAH20
PRG1_PRU0_GPI13PRU_ICSSG PRU Data InputIAH21
PRG1_PRU0_GPI14PRU_ICSSG PRU Data InputIAG20
PRG1_PRU0_GPI15PRU_ICSSG PRU Data InputIAD19
PRG1_PRU0_GPI16PRU_ICSSG PRU Data InputIAD20
PRG1_PRU0_GPI17PRU_ICSSG PRU Data InputIAH26
PRG1_PRU0_GPI18PRU_ICSSG PRU Data InputIAG25
PRG1_PRU0_GPI19PRU_ICSSG PRU Data InputIAG26
PRG1_PRU0_GPO0PRU_ICSSG PRU Data OutputIOAE22
PRG1_PRU0_GPO1PRU_ICSSG PRU Data OutputIOAG24
PRG1_PRU0_GPO2PRU_ICSSG PRU Data OutputIOAF23
PRG1_PRU0_GPO3PRU_ICSSG PRU Data OutputIOAD21
PRG1_PRU0_GPO4PRU_ICSSG PRU Data OutputIOAG23
PRG1_PRU0_GPO5PRU_ICSSG PRU Data OutputIOAF27
PRG1_PRU0_GPO6PRU_ICSSG PRU Data OutputIOAF22
PRG1_PRU0_GPO7PRU_ICSSG PRU Data OutputIOAG27
PRG1_PRU0_GPO8PRU_ICSSG PRU Data OutputIOAF28
PRG1_PRU0_GPO9PRU_ICSSG PRU Data OutputIOAF26
PRG1_PRU0_GPO10PRU_ICSSG PRU Data OutputIOAH25
PRG1_PRU0_GPO11PRU_ICSSG PRU Data OutputIOAF21, AH20
PRG1_PRU0_GPO12PRU_ICSSG PRU Data OutputIOAH20, AH21
PRG1_PRU0_GPO13PRU_ICSSG PRU Data OutputIOAG20, AH21
PRG1_PRU0_GPO14PRU_ICSSG PRU Data OutputIOAD19, AG20
PRG1_PRU0_GPO15PRU_ICSSG PRU Data OutputIOAD19, AF21
PRG1_PRU0_GPO16PRU_ICSSG PRU Data OutputIOAD20
PRG1_PRU0_GPO17PRU_ICSSG PRU Data OutputIOAH26
PRG1_PRU0_GPO18PRU_ICSSG PRU Data OutputIOAG25
PRG1_PRU0_GPO19PRU_ICSSG PRU Data OutputIOAG26
PRG1_PRU1_GPI0PRU_ICSSG PRU Data InputIAH24
PRG1_PRU1_GPI1PRU_ICSSG PRU Data InputIAH23
PRG1_PRU1_GPI2PRU_ICSSG PRU Data InputIAG21
PRG1_PRU1_GPI3PRU_ICSSG PRU Data InputIAH22
PRG1_PRU1_GPI4PRU_ICSSG PRU Data InputIAE21
PRG1_PRU1_GPI5PRU_ICSSG PRU Data InputIAC22
PRG1_PRU1_GPI6PRU_ICSSG PRU Data InputIAG22
PRG1_PRU1_GPI7PRU_ICSSG PRU Data InputIAD23
PRG1_PRU1_GPI8PRU_ICSSG PRU Data InputIAE24
PRG1_PRU1_GPI9PRU_ICSSG PRU Data InputIAF25
PRG1_PRU1_GPI10PRU_ICSSG PRU Data InputIAF24
PRG1_PRU1_GPI11PRU_ICSSG PRU Data InputIAC20
PRG1_PRU1_GPI12PRU_ICSSG PRU Data InputIAE20
PRG1_PRU1_GPI13PRU_ICSSG PRU Data InputIAF19
PRG1_PRU1_GPI14PRU_ICSSG PRU Data InputIAH19
PRG1_PRU1_GPI15PRU_ICSSG PRU Data InputIAG19
PRG1_PRU1_GPI16PRU_ICSSG PRU Data InputIAE19
PRG1_PRU1_GPI17PRU_ICSSG PRU Data InputIAE23
PRG1_PRU1_GPI18PRU_ICSSG PRU Data InputIAD22
PRG1_PRU1_GPI19PRU_ICSSG PRU Data InputIAC21
PRG1_PRU1_GPO0PRU_ICSSG PRU Data OutputIOAH24
PRG1_PRU1_GPO1PRU_ICSSG PRU Data OutputIOAH23
PRG1_PRU1_GPO2PRU_ICSSG PRU Data OutputIOAG21
PRG1_PRU1_GPO3PRU_ICSSG PRU Data OutputIOAH22
PRG1_PRU1_GPO4PRU_ICSSG PRU Data OutputIOAE21
PRG1_PRU1_GPO5PRU_ICSSG PRU Data OutputIOAC22
PRG1_PRU1_GPO6PRU_ICSSG PRU Data OutputIOAG22
PRG1_PRU1_GPO7PRU_ICSSG PRU Data OutputIOAD23
PRG1_PRU1_GPO8PRU_ICSSG PRU Data OutputIOAE24
PRG1_PRU1_GPO9PRU_ICSSG PRU Data OutputIOAF25
PRG1_PRU1_GPO10PRU_ICSSG PRU Data OutputIOAF24
PRG1_PRU1_GPO11PRU_ICSSG PRU Data OutputIOAC20, AE20
PRG1_PRU1_GPO12PRU_ICSSG PRU Data OutputIOAE20, AF19
PRG1_PRU1_GPO13PRU_ICSSG PRU Data OutputIOAF19, AH19
PRG1_PRU1_GPO14PRU_ICSSG PRU Data OutputIOAG19, AH19
PRG1_PRU1_GPO15PRU_ICSSG PRU Data OutputIOAC20, AG19
PRG1_PRU1_GPO16PRU_ICSSG PRU Data OutputIOAE19
PRG1_PRU1_GPO17PRU_ICSSG PRU Data OutputIOAE23
PRG1_PRU1_GPO18PRU_ICSSG PRU Data OutputIOAD22
PRG1_PRU1_GPO19PRU_ICSSG PRU Data OutputIOAC21
PRG1_PWM0_TZ_INPRU_ICSSG PWM Trip Zone InputIAG25
PRG1_PWM0_TZ_OUTPRU_ICSSG PWM Trip Zone OutputOAG26
PRG1_PWM1_TZ_INPRU_ICSSG PWM Trip Zone InputIAD22
PRG1_PWM1_TZ_OUTPRU_ICSSG PWM Trip Zone OutputOAC21
PRG1_PWM2_TZ_INPRU_ICSSG PWM Trip Zone InputIAF24
PRG1_PWM2_TZ_OUTPRU_ICSSG PWM Trip Zone OutputOAE24
PRG1_PWM3_TZ_INPRU_ICSSG PWM Trip Zone InputIAF26
PRG1_PWM3_TZ_OUTPRU_ICSSG PWM Trip Zone OutputOAF21
PRG1_PWM0_A0PRU_ICSSG PWM Output AIOAH20
PRG1_PWM0_A1PRU_ICSSG PWM Output AIOAG20
PRG1_PWM0_A2PRU_ICSSG PWM Output AIOAD20
PRG1_PWM0_B0PRU_ICSSG PWM Output BIOAH21
PRG1_PWM0_B1PRU_ICSSG PWM Output BIOAD19
PRG1_PWM0_B2PRU_ICSSG PWM Output BIOAH26
PRG1_PWM1_A0PRU_ICSSG PWM Output AIOAE20
PRG1_PWM1_A1PRU_ICSSG PWM Output AIOAH19
PRG1_PWM1_A2PRU_ICSSG PWM Output AIOAE19
PRG1_PWM1_B0PRU_ICSSG PWM Output BIOAF19
PRG1_PWM1_B1PRU_ICSSG PWM Output BIOAG19
PRG1_PWM1_B2PRU_ICSSG PWM Output BIOAE23
PRG1_PWM2_A0PRU_ICSSG PWM Output AIOAF23
PRG1_PWM2_A1PRU_ICSSG PWM Output AIOAF28
PRG1_PWM2_A2PRU_ICSSG PWM Output AIOAG21
PRG1_PWM2_B0PRU_ICSSG PWM Output BIOAG23
PRG1_PWM2_B1PRU_ICSSG PWM Output BIOAH25
PRG1_PWM2_B2PRU_ICSSG PWM Output BIOAE21
PRG1_PWM3_A0PRU_ICSSG PWM Output AIOAE22
PRG1_PWM3_A1PRU_ICSSG PWM Output AIOAF22
PRG1_PWM3_A2PRU_ICSSG PWM Output AIOAD21
PRG1_PWM3_B0PRU_ICSSG PWM Output BIOAG24
PRG1_PWM3_B1PRU_ICSSG PWM Output BIOAG27
PRG1_PWM3_B2PRU_ICSSG PWM Output BIOAF27
PRG1_RGMII1_RXCPRU_ICSSG RGMII Receive ClockIAF22
PRG1_RGMII1_RX_CTLPRU_ICSSG RGMII Receive ControlIAG23
PRG1_RGMII1_TXCPRU_ICSSG RGMII Transmit ClockIOAD20
PRG1_RGMII1_TX_CTLPRU_ICSSG RGMII Transmit ControlOAF21
PRG1_RGMII2_RXCPRU_ICSSG RGMII Receive ClockIAG22
PRG1_RGMII2_RX_CTLPRU_ICSSG RGMII Receive ControlIAE21
PRG1_RGMII2_TXCPRU_ICSSG RGMII Transmit ClockIOAE19
PRG1_RGMII2_TX_CTLPRU_ICSSG RGMII Transmit ControlOAC20
PRG1_RGMII1_RD0PRU_ICSSG RGMII Receive DataIAE22
PRG1_RGMII1_RD1PRU_ICSSG RGMII Receive DataIAG24
PRG1_RGMII1_RD2PRU_ICSSG RGMII Receive DataIAF23
PRG1_RGMII1_RD3PRU_ICSSG RGMII Receive DataIAD21
PRG1_RGMII1_TD0PRU_ICSSG RGMII Transmit DataOAH20
PRG1_RGMII1_TD1PRU_ICSSG RGMII Transmit DataOAH21
PRG1_RGMII1_TD2PRU_ICSSG RGMII Transmit DataOAG20
PRG1_RGMII1_TD3PRU_ICSSG RGMII Transmit DataOAD19
PRG1_RGMII2_RD0PRU_ICSSG RGMII Receive DataIAH24
PRG1_RGMII2_RD1PRU_ICSSG RGMII Receive DataIAH23
PRG1_RGMII2_RD2PRU_ICSSG RGMII Receive DataIAG21
PRG1_RGMII2_RD3PRU_ICSSG RGMII Receive DataIAH22
PRG1_RGMII2_TD0PRU_ICSSG RGMII Transmit DataOAE20
PRG1_RGMII2_TD1PRU_ICSSG RGMII Transmit DataOAF19
PRG1_RGMII2_TD2PRU_ICSSG RGMII Transmit DataOAH19
PRG1_RGMII2_TD3PRU_ICSSG RGMII Transmit DataOAG19
PRG1_UART0_CTSnPRU_ICSSG UART Clear to Send (active low)IAF26
PRG1_UART0_RTSnPRU_ICSSG UART Request to Send (active low)OAH25
PRG1_UART0_RXDPRU_ICSSG UART Receive DataIAF25
PRG1_UART0_TXDPRU_ICSSG UART Transmit DataOAF24
Table 5-55 PRU_ICSSG2 Signal Descriptions
SIGNAL NAME [1]DESCRIPTION [2]PIN TYPE [3]BALL [4]
PRG2_ECAP0_IN_APWM_OUTPRU_ICSSG Enhanced Capture (ECAP) Input or Auxiliary PWM (APWM) OuputIOAE16
PRG2_ECAP0_SYNC_INPRU_ICSSG ECAP Sync InputIAD14
PRG2_ECAP0_SYNC_OUTPRU_ICSSG ECAP Sync OutputOAG14
PRG2_IEP0_EDIO_OUTVALIDPRU_ICSSG Industrial Ethernet Digital I/O OutvalidO(1)A23
PRG2_IEP0_EDC_LATCH_IN0PRU_ICSSG Industrial Ethernet Distributed Clock Latch InputIAD12
PRG2_IEP0_EDC_LATCH_IN1PRU_ICSSG Industrial Ethernet Distributed Clock Latch InputIAE12
PRG2_IEP0_EDC_SYNC_OUT0PRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputOAH12
PRG2_IEP0_EDC_SYNC_OUT1PRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputOAF12
PRG2_IEP0_EDIO_DATA_IN_OUT28PRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputIOR23
PRG2_IEP0_EDIO_DATA_IN_OUT29PRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputIOT24
PRG2_IEP0_EDIO_DATA_IN_OUT30PRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputIOR25
PRG2_IEP0_EDIO_DATA_IN_OUT31PRU_ICSSG Industrial Ethernet Digital I/O Data Input/OutputIOT27
PRG2_IEP1_EDC_LATCH_IN0PRU_ICSSG Industrial Ethernet Distributed Clock Latch InputIR23
PRG2_IEP1_EDC_LATCH_IN1PRU_ICSSG Industrial Ethernet Distributed Clock Latch InputIR25
PRG2_IEP1_EDC_SYNC_OUT0PRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputOT24
PRG2_IEP1_EDC_SYNC_OUT1PRU_ICSSG Industrial Ethernet Distributed Clock Sync OutputOT27
PRG2_MDIO0_MDCPRU_ICSSG MDIO ClockOAE15
PRG2_MDIO0_MDIOPRU_ICSSG MDIO DataIOAC19
PRG2_PRU0_GPI0PRU_ICSSG PRU Data InputIAF18
PRG2_PRU0_GPI1PRU_ICSSG PRU Data InputIAE18
PRG2_PRU0_GPI2PRU_ICSSG PRU Data InputIAH17
PRG2_PRU0_GPI3PRU_ICSSG PRU Data InputIAG18
PRG2_PRU0_GPI4PRU_ICSSG PRU Data InputIAG17
PRG2_PRU0_GPI5PRU_ICSSG PRU Data InputIAF17
PRG2_PRU0_GPI6PRU_ICSSG PRU Data InputIAE17
PRG2_PRU0_GPI7PRU_ICSSG PRU Data InputIAC19
PRG2_PRU0_GPI8PRU_ICSSG PRU Data InputIAH16
PRG2_PRU0_GPI9PRU_ICSSG PRU Data InputIAG16
PRG2_PRU0_GPI10PRU_ICSSG PRU Data InputIAF16
PRG2_PRU0_GPI11PRU_ICSSG PRU Data InputIAE16
PRG2_PRU0_GPI12PRU_ICSSG PRU Data InputIN23
PRG2_PRU0_GPI13PRU_ICSSG PRU Data InputIM26
PRG2_PRU0_GPI14PRU_ICSSG PRU Data InputIP28
PRG2_PRU0_GPI15PRU_ICSSG PRU Data InputIP27
PRG2_PRU0_GPI16PRU_ICSSG PRU Data InputIAD16
PRG2_PRU0_GPI17PRU_ICSSG PRU Data InputIP23
PRG2_PRU0_GPO0PRU_ICSSG PRU Data OutputIOAF18
PRG2_PRU0_GPO1PRU_ICSSG PRU Data OutputIOAE18
PRG2_PRU0_GPO2PRU_ICSSG PRU Data OutputIOAH17
PRG2_PRU0_GPO3PRU_ICSSG PRU Data OutputIOAG18
PRG2_PRU0_GPO4PRU_ICSSG PRU Data OutputIOAG17
PRG2_PRU0_GPO5PRU_ICSSG PRU Data OutputIOAF17
PRG2_PRU0_GPO6PRU_ICSSG PRU Data OutputIOAE17
PRG2_PRU0_GPO7PRU_ICSSG PRU Data OutputIOAC19
PRG2_PRU0_GPO8PRU_ICSSG PRU Data OutputIOAH16
PRG2_PRU0_GPO9PRU_ICSSG PRU Data OutputIOAG16
PRG2_PRU0_GPO10PRU_ICSSG PRU Data OutputIOAF16
PRG2_PRU0_GPO11PRU_ICSSG PRU Data OutputIOAE16
PRG2_PRU0_GPO12PRU_ICSSG PRU Data OutputION23
PRG2_PRU0_GPO13PRU_ICSSG PRU Data OutputIOM26
PRG2_PRU0_GPO14PRU_ICSSG PRU Data OutputIOP28
PRG2_PRU0_GPO15PRU_ICSSG PRU Data OutputIOP27
PRG2_PRU0_GPO16PRU_ICSSG PRU Data OutputIOAD16
PRG2_PRU0_GPO17PRU_ICSSG PRU Data OutputIOP23
PRG2_PRU1_GPI0PRU_ICSSG PRU Data InputIAH15
PRG2_PRU1_GPI1PRU_ICSSG PRU Data InputIAC16
PRG2_PRU1_GPI2PRU_ICSSG PRU Data InputIAD17
PRG2_PRU1_GPI3PRU_ICSSG PRU Data InputIAH14
PRG2_PRU1_GPI4PRU_ICSSG PRU Data InputIAG14
PRG2_PRU1_GPI5PRU_ICSSG PRU Data InputIAG15
PRG2_PRU1_GPI6PRU_ICSSG PRU Data InputIAC17
PRG2_PRU1_GPI7PRU_ICSSG PRU Data InputIAE15
PRG2_PRU1_GPI8PRU_ICSSG PRU Data InputIAD15
PRG2_PRU1_GPI9PRU_ICSSG PRU Data InputIAF14
PRG2_PRU1_GPI10PRU_ICSSG PRU Data InputIAC15
PRG2_PRU1_GPI11PRU_ICSSG PRU Data InputIAD14
PRG2_PRU1_GPI12PRU_ICSSG PRU Data InputIN26
PRG2_PRU1_GPI13PRU_ICSSG PRU Data InputIN25
PRG2_PRU1_GPI14PRU_ICSSG PRU Data InputIP24
PRG2_PRU1_GPI15PRU_ICSSG PRU Data InputIR27
PRG2_PRU1_GPI16PRU_ICSSG PRU Data InputIAE14
PRG2_PRU1_GPI17PRU_ICSSG PRU Data InputIT23
PRG2_PRU1_GPO0PRU_ICSSG PRU Data OutputIOAH15
PRG2_PRU1_GPO1PRU_ICSSG PRU Data OutputIOAC16
PRG2_PRU1_GPO2PRU_ICSSG PRU Data OutputIOAD17
PRG2_PRU1_GPO3PRU_ICSSG PRU Data OutputIOAH14
PRG2_PRU1_GPO4PRU_ICSSG PRU Data OutputIOAG14
PRG2_PRU1_GPO5PRU_ICSSG PRU Data OutputIOAG15
PRG2_PRU1_GPO6PRU_ICSSG PRU Data OutputIOAC17
PRG2_PRU1_GPO7PRU_ICSSG PRU Data OutputIOAE15
PRG2_PRU1_GPO8PRU_ICSSG PRU Data OutputIOAD15
PRG2_PRU1_GPO9PRU_ICSSG PRU Data OutputIOAF14
PRG2_PRU1_GPO10PRU_ICSSG PRU Data OutputIOAC15
PRG2_PRU1_GPO11PRU_ICSSG PRU Data OutputIOAD14
PRG2_PRU1_GPO12PRU_ICSSG PRU Data OutputION26
PRG2_PRU1_GPO13PRU_ICSSG PRU Data OutputION25
PRG2_PRU1_GPO14PRU_ICSSG PRU Data OutputIOP24
PRG2_PRU1_GPO15PRU_ICSSG PRU Data OutputIOR27
PRG2_PRU1_GPO16PRU_ICSSG PRU Data OutputIOAE14
PRG2_PRU1_GPO17PRU_ICSSG PRU Data OutputIOT23
PRG2_PWM0_TZ_INPRU_ICSSG PWM Trip Zone InputIP28
PRG2_PWM0_TZ_OUTPRU_ICSSG PWM Trip Zone OutputOP24
PRG2_PWM1_TZ_INPRU_ICSSG PWM Trip Zone InputIF18
PRG2_PWM1_TZ_OUTPRU_ICSSG PWM Trip Zone OutputOAE14
PRG2_PWM2_TZ_INPRU_ICSSG PWM Trip Zone InputIP23
PRG2_PWM2_TZ_OUTPRU_ICSSG PWM Trip Zone OutputOT23
PRG2_PWM3_TZ_INPRU_ICSSG PWM Trip Zone InputIAE15
PRG2_PWM3_TZ_OUTPRU_ICSSG PWM Trip Zone OutputOAF14
PRG2_PWM0_A0PRU_ICSSG PWM Output AIOAG17
PRG2_PWM0_A1PRU_ICSSG PWM Output AIOAD16
PRG2_PWM0_A2PRU_ICSSG PWM Output AIOAD15
PRG2_PWM0_B0PRU_ICSSG PWM Output BIOAH16
PRG2_PWM0_B1PRU_ICSSG PWM Output BIOAD17
PRG2_PWM0_B2PRU_ICSSG PWM Output BIOAC15
PRG2_PWM1_A0PRU_ICSSG PWM Output AIOR23
PRG2_PWM1_A1PRU_ICSSG PWM Output AIOAD18
PRG2_PWM1_A2PRU_ICSSG PWM Output AIOAE26
PRG2_PWM1_B0PRU_ICSSG PWM Output BIOT24
PRG2_PWM1_B1PRU_ICSSG PWM Output BIOAH18
PRG2_PWM1_B2PRU_ICSSG PWM Output BIOAE28
PRG2_PWM2_A0PRU_ICSSG PWM Output AION23
PRG2_PWM2_A1PRU_ICSSG PWM Output AIOP27
PRG2_PWM2_A2PRU_ICSSG PWM Output AION25
PRG2_PWM2_B0PRU_ICSSG PWM Output BIOM26
PRG2_PWM2_B1PRU_ICSSG PWM Output BION26
PRG2_PWM2_B2PRU_ICSSG PWM Output BIOR27
PRG2_PWM3_A0PRU_ICSSG PWM Output AIOAF18
PRG2_PWM3_A1PRU_ICSSG PWM Output AIOAF17
PRG2_PWM3_A2PRU_ICSSG PWM Output AIOAH15
PRG2_PWM3_B0PRU_ICSSG PWM Output BIOAG18
PRG2_PWM3_B1PRU_ICSSG PWM Output BIOAE17
PRG2_PWM3_B2PRU_ICSSG PWM Output BIOAC16
PRG2_RGMII1_RXCPRU_ICSSG RGMII Receive ClockIAF17
PRG2_RGMII1_RX_CTLPRU_ICSSG RGMII Receive ControlIAG17
PRG2_RGMII1_TXCPRU_ICSSG RGMII Transmit ClockIOAD16
PRG2_RGMII1_TX_CTLPRU_ICSSG RGMII Transmit ControlOAE17
PRG2_RGMII2_RXCPRU_ICSSG RGMII Receive ClockIAG15
PRG2_RGMII2_RX_CTLPRU_ICSSG RGMII Receive ControlIAG14
PRG2_RGMII2_TXCPRU_ICSSG RGMII Transmit ClockIOAE14
PRG2_RGMII2_TX_CTLPRU_ICSSG RGMII Transmit ControlOAC17
PRG2_RGMII1_RD0PRU_ICSSG RGMII Receive DataIAF18
PRG2_RGMII1_RD1PRU_ICSSG RGMII Receive DataIAE18
PRG2_RGMII1_RD2PRU_ICSSG RGMII Receive DataIAH17
PRG2_RGMII1_RD3PRU_ICSSG RGMII Receive DataIAG18
PRG2_RGMII1_TD0PRU_ICSSG RGMII Transmit DataOAH16
PRG2_RGMII1_TD1PRU_ICSSG RGMII Transmit DataOAG16
PRG2_RGMII1_TD2PRU_ICSSG RGMII Transmit DataOAF16
PRG2_RGMII1_TD3PRU_ICSSG RGMII Transmit DataOAE16
PRG2_RGMII2_RD0PRU_ICSSG RGMII Receive DataIAH15
PRG2_RGMII2_RD1PRU_ICSSG RGMII Receive DataIAC16
PRG2_RGMII2_RD2PRU_ICSSG RGMII Receive DataIAD17
PRG2_RGMII2_RD3PRU_ICSSG RGMII Receive DataIAH14
PRG2_RGMII2_TD0PRU_ICSSG RGMII Transmit DataOAD15
PRG2_RGMII2_TD1PRU_ICSSG RGMII Transmit DataOAF14
PRG2_RGMII2_TD2PRU_ICSSG RGMII Transmit DataOAC15
PRG2_RGMII2_TD3PRU_ICSSG RGMII Transmit DataOAD14
PRG2_UART0_CTSnPRU_ICSSG UART Clear to Send (active low)IAD12
PRG2_UART0_RTSnPRU_ICSSG UART Request to Send (active low)OAH12
PRG2_UART0_RXDPRU_ICSSG UART Receive DataIAE12
PRG2_UART0_TXDPRU_ICSSG UART Transmit DataOAF12
(1) When OSC1 is being used with an external crystal, this signal is unavailable. The output functionality must be disabled.